diff mbox series

[2/5] clk: imx: clk-imx8qxp-lpcg: Add display controller LPCG clocks support

Message ID 1605688290-21805-3-git-send-email-victor.liu@nxp.com
State New
Headers show
Series Add some clocks support for i.MX8qxp DC0/MIPI-LVDS subsystems | expand

Commit Message

Liu Ying Nov. 18, 2020, 8:31 a.m. UTC 
This patch adds LPCG clocks support for display controller of i.MX8qxp SoC.

Cc: Michael Turquette <mturquette@baylibre.com>
Cc: Stephen Boyd <sboyd@kernel.org>
Cc: Shawn Guo <shawnguo@kernel.org>
Cc: Sascha Hauer <s.hauer@pengutronix.de>
Cc: Pengutronix Kernel Team <kernel@pengutronix.de>
Cc: Fabio Estevam <festevam@gmail.com>
Cc: NXP Linux Team <linux-imx@nxp.com>
Cc: Rob Herring <robh+dt@kernel.org>
Cc: Dong Aisheng <aisheng.dong@nxp.com>
Signed-off-by: Liu Ying <victor.liu@nxp.com>
---
 drivers/clk/imx/clk-imx8qxp-lpcg.c     | 41 ++++++++++++++++++++++++++++++++++
 drivers/clk/imx/clk-imx8qxp-lpcg.h     | 20 +++++++++++++++++
 include/dt-bindings/clock/imx8-clock.h | 35 +++++++++++++++++++++++++++++
 3 files changed, 96 insertions(+)
diff mbox series

Patch

diff --git a/drivers/clk/imx/clk-imx8qxp-lpcg.c b/drivers/clk/imx/clk-imx8qxp-lpcg.c
index d3e905c..176d426 100644
--- a/drivers/clk/imx/clk-imx8qxp-lpcg.c
+++ b/drivers/clk/imx/clk-imx8qxp-lpcg.c
@@ -115,6 +115,46 @@  static const struct imx8qxp_ss_lpcg imx8qxp_ss_conn = {
 	.num_max = IMX_CONN_LPCG_CLK_END,
 };
 
+static const struct imx8qxp_lpcg_data imx8qxp_lpcg_dc[] = {
+	{ IMX_DC0_LPCG_DISP0_CLK, "dc0_lpcg_disp0_clk", "dc0_disp0_clk", 0, DC_DISP_LPCG, 0, 0, },
+	{ IMX_DC0_LPCG_DISP1_CLK, "dc0_lpcg_disp1_clk", "dc0_disp1_clk", 0, DC_DISP_LPCG, 4, 0, },
+	{ IMX_DC0_LPCG_LIS_IPG_CLK, "dc0_lpcg_lis_ipg_clk", "dc_cfg_clk_root", 0, DC_LIS_IPG_LPCG, 16, 0, },
+	{ IMX_DC0_LPCG_DISP_CTL_LINK_MST0_CLK, "dc0_lpcg_disp_ctl_link_mst0_clk", "dc_cfg_clk_root", 0, DC_DISP_CTL_LINK_MST0_LPCG, 16, 0, },
+	{ IMX_DC0_LPCG_PIX_COMBINER_APB_CLK, "dc0_lpcg_pix_combiner_apb_clk", "dc_cfg_clk_root", 0, DC_PIX_COMBINER_APB_LPCG, 16, 0, },
+	{ IMX_DC0_LPCG_DC_AXI_CLK, "dc0_lpcg_dc_axi_clk", "dc_axi_int_clk_root", 0, DC_AXI_CFG_LPCG, 20, 0, },
+	{ IMX_DC0_LPCG_DC_CFG_CLK, "dc0_lpcg_dc_cfg_clk", "dc_cfg_clk_root", 0, DC_AXI_CFG_LPCG, 16, 0, },
+	{ IMX_DC0_LPCG_DPR0_APB_CLK, "dc0_lpcg_dpr0_apb_clk", "dc_cfg_clk_root", 0, DC_DPR0_LPCG, 16, 0, },
+	{ IMX_DC0_LPCG_DPR0_B_CLK, "dc0_lpcg_dpr0_b_clk", "dc_axi_ext_clk_root", 0, DC_DPR0_LPCG, 20, 0, },
+	{ IMX_DC0_LPCG_RTRAM0_CLK, "dc0_lpcg_rtram0_clk", "dc_axi_int_clk_root", 0, DC_RTRAM0_LPCG, 0, 0, },
+	{ IMX_DC0_LPCG_PRG0_RTRAM_CLK, "dc0_lpcg_prg0_rtram_clk", "dc_axi_int_clk_root", 0, DC_PRG0_LPCG, 0, 0, },
+	{ IMX_DC0_LPCG_PRG0_APB_CLK, "dc0_lpcg_prg0_apb_clk", "dc_cfg_clk_root", 0, DC_PRG0_LPCG, 16, 0, },
+	{ IMX_DC0_LPCG_PRG1_RTRAM_CLK, "dc0_lpcg_prg1_rtram_clk", "dc_axi_int_clk_root", 0, DC_PRG1_LPCG, 0, 0, },
+	{ IMX_DC0_LPCG_PRG1_APB_CLK, "dc0_lpcg_prg1_apb_clk", "dc_cfg_clk_root", 0, DC_PRG1_LPCG, 16, 0, },
+	{ IMX_DC0_LPCG_PRG2_RTRAM_CLK, "dc0_lpcg_prg2_rtram_clk", "dc_axi_int_clk_root", 0, DC_PRG2_LPCG, 0, 0, },
+	{ IMX_DC0_LPCG_PRG2_APB_CLK, "dc0_lpcg_prg2_apb_clk", "dc_cfg_clk_root", 0, DC_PRG2_LPCG, 16, 0, },
+	{ IMX_DC0_LPCG_DPR1_APB_CLK, "dc0_lpcg_dpr1_apb_clk", "dc_cfg_clk_root", 0, DC_DPR1_LPCG, 16, 0, },
+	{ IMX_DC0_LPCG_DPR1_B_CLK, "dc0_lpcg_dpr1_b_clk", "dc_axi_ext_clk_root", 0, DC_DPR1_LPCG, 20, 0, },
+	{ IMX_DC0_LPCG_RTRAM1_CLK, "dc0_lpcg_rtram1_clk", "dc_axi_int_clk_root", 0, DC_RTRAM1_LPCG, 0, 0, },
+	{ IMX_DC0_LPCG_PRG3_RTRAM_CLK, "dc0_lpcg_prg3_rtram_clk", "dc_axi_int_clk_root", 0, DC_PRG3_LPCG, 0, 0, },
+	{ IMX_DC0_LPCG_PRG3_APB_CLK, "dc0_lpcg_prg3_apb_clk", "dc_cfg_clk_root", 0, DC_PRG3_LPCG, 16, 0, },
+	{ IMX_DC0_LPCG_PRG4_RTRAM_CLK, "dc0_lpcg_prg4_rtram_clk", "dc_axi_int_clk_root", 0, DC_PRG4_LPCG, 0, 0, },
+	{ IMX_DC0_LPCG_PRG4_APB_CLK, "dc0_lpcg_prg4_apb_clk", "dc_cfg_clk_root", 0, DC_PRG4_LPCG, 16, 0, },
+	{ IMX_DC0_LPCG_PRG5_RTRAM_CLK, "dc0_lpcg_prg5_rtram_clk", "dc_axi_int_clk_root", 0, DC_PRG5_LPCG, 0, 0, },
+	{ IMX_DC0_LPCG_PRG5_APB_CLK, "dc0_lpcg_prg5_apb_clk", "dc_cfg_clk_root", 0, DC_PRG5_LPCG, 16, 0, },
+	{ IMX_DC0_LPCG_PRG6_RTRAM_CLK, "dc0_lpcg_prg6_rtram_clk", "dc_axi_int_clk_root", 0, DC_PRG6_LPCG, 0, 0, },
+	{ IMX_DC0_LPCG_PRG6_APB_CLK, "dc0_lpcg_prg6_apb_clk", "dc_cfg_clk_root", 0, DC_PRG6_LPCG, 16, 0, },
+	{ IMX_DC0_LPCG_PRG7_RTRAM_CLK, "dc0_lpcg_prg7_rtram_clk", "dc_axi_int_clk_root", 0, DC_PRG7_LPCG, 0, 0, },
+	{ IMX_DC0_LPCG_PRG7_APB_CLK, "dc0_lpcg_prg7_apb_clk", "dc_cfg_clk_root", 0, DC_PRG7_LPCG, 16, 0, },
+	{ IMX_DC0_LPCG_PRG8_RTRAM_CLK, "dc0_lpcg_prg8_rtram_clk", "dc_axi_int_clk_root", 0, DC_PRG8_LPCG, 0, 0, },
+	{ IMX_DC0_LPCG_PRG8_APB_CLK, "dc0_lpcg_prg8_apb_clk", "dc_cfg_clk_root", 0, DC_PRG8_LPCG, 16, 0, },
+};
+
+static const struct imx8qxp_ss_lpcg imx8qxp_ss_dc = {
+	.lpcg = imx8qxp_lpcg_dc,
+	.num_lpcg = ARRAY_SIZE(imx8qxp_lpcg_dc),
+	.num_max = IMX_DC0_LPCG_CLK_END,
+};
+
 static const struct imx8qxp_lpcg_data imx8qxp_lpcg_lsio[] = {
 	{ IMX_LSIO_LPCG_PWM0_IPG_CLK, "pwm0_lpcg_ipg_clk", "pwm0_clk", 0, LSIO_PWM_0_LPCG, 0, 0, },
 	{ IMX_LSIO_LPCG_PWM0_IPG_HF_CLK, "pwm0_lpcg_ipg_hf_clk", "pwm0_clk", 0, LSIO_PWM_0_LPCG, 4, 0, },
@@ -355,6 +395,7 @@  static int imx8qxp_lpcg_clk_probe(struct platform_device *pdev)
 static const struct of_device_id imx8qxp_lpcg_match[] = {
 	{ .compatible = "fsl,imx8qxp-lpcg-adma", &imx8qxp_ss_adma, },
 	{ .compatible = "fsl,imx8qxp-lpcg-conn", &imx8qxp_ss_conn, },
+	{ .compatible = "fsl,imx8qxp-lpcg-dc", &imx8qxp_ss_dc, },
 	{ .compatible = "fsl,imx8qxp-lpcg-lsio", &imx8qxp_ss_lsio, },
 	{ .compatible = "fsl,imx8qxp-lpcg", NULL },
 	{ /* sentinel */ }
diff --git a/drivers/clk/imx/clk-imx8qxp-lpcg.h b/drivers/clk/imx/clk-imx8qxp-lpcg.h
index 2a37ce5..e1423a9 100644
--- a/drivers/clk/imx/clk-imx8qxp-lpcg.h
+++ b/drivers/clk/imx/clk-imx8qxp-lpcg.h
@@ -99,4 +99,24 @@ 
 #define ADMA_FLEXCAN_1_LPCG		0x1ce0000
 #define ADMA_FLEXCAN_2_LPCG		0x1cf0000
 
+/* Display SS */
+#define DC_DISP_LPCG			0x00
+#define DC_LIS_IPG_LPCG			0x04
+#define DC_DISP_CTL_LINK_MST0_LPCG	0x08
+#define DC_PIX_COMBINER_APB_LPCG	0x10
+#define DC_AXI_CFG_LPCG			0x14
+#define DC_DPR0_LPCG			0x18
+#define DC_RTRAM0_LPCG			0x1c
+#define DC_PRG0_LPCG			0x20
+#define DC_PRG1_LPCG			0x24
+#define DC_PRG2_LPCG			0x28
+#define DC_DPR1_LPCG			0x2c
+#define DC_RTRAM1_LPCG			0x30
+#define DC_PRG3_LPCG			0x34
+#define DC_PRG4_LPCG			0x38
+#define DC_PRG5_LPCG			0x3c
+#define DC_PRG6_LPCG			0x40
+#define DC_PRG7_LPCG			0x44
+#define DC_PRG8_LPCG			0x48
+
 #endif /* _IMX8QXP_LPCG_H */
diff --git a/include/dt-bindings/clock/imx8-clock.h b/include/dt-bindings/clock/imx8-clock.h
index 673a8c6..c9dd0c6 100644
--- a/include/dt-bindings/clock/imx8-clock.h
+++ b/include/dt-bindings/clock/imx8-clock.h
@@ -290,4 +290,39 @@ 
 
 #define IMX_ADMA_LPCG_CLK_END				45
 
+/* DC0 SS LPCG */
+#define IMX_DC0_LPCG_DISP0_CLK				0
+#define IMX_DC0_LPCG_DISP1_CLK				1
+#define IMX_DC0_LPCG_LIS_IPG_CLK			2
+#define IMX_DC0_LPCG_DISP_CTL_LINK_MST0_CLK		3
+#define IMX_DC0_LPCG_PIX_COMBINER_APB_CLK		4
+#define IMX_DC0_LPCG_DC_AXI_CLK				5
+#define IMX_DC0_LPCG_DC_CFG_CLK				6
+#define IMX_DC0_LPCG_DPR0_APB_CLK			7
+#define IMX_DC0_LPCG_DPR0_B_CLK				8
+#define IMX_DC0_LPCG_RTRAM0_CLK				9
+#define IMX_DC0_LPCG_PRG0_RTRAM_CLK			10
+#define IMX_DC0_LPCG_PRG0_APB_CLK			11
+#define IMX_DC0_LPCG_PRG1_RTRAM_CLK			12
+#define IMX_DC0_LPCG_PRG1_APB_CLK			13
+#define IMX_DC0_LPCG_PRG2_RTRAM_CLK			14
+#define IMX_DC0_LPCG_PRG2_APB_CLK			15
+#define IMX_DC0_LPCG_DPR1_APB_CLK			16
+#define IMX_DC0_LPCG_DPR1_B_CLK				17
+#define IMX_DC0_LPCG_RTRAM1_CLK				18
+#define IMX_DC0_LPCG_PRG3_RTRAM_CLK			19
+#define IMX_DC0_LPCG_PRG3_APB_CLK			20
+#define IMX_DC0_LPCG_PRG4_RTRAM_CLK			21
+#define IMX_DC0_LPCG_PRG4_APB_CLK			22
+#define IMX_DC0_LPCG_PRG5_RTRAM_CLK			23
+#define IMX_DC0_LPCG_PRG5_APB_CLK			24
+#define IMX_DC0_LPCG_PRG6_RTRAM_CLK			25
+#define IMX_DC0_LPCG_PRG6_APB_CLK			26
+#define IMX_DC0_LPCG_PRG7_RTRAM_CLK			27
+#define IMX_DC0_LPCG_PRG7_APB_CLK			28
+#define IMX_DC0_LPCG_PRG8_RTRAM_CLK			29
+#define IMX_DC0_LPCG_PRG8_APB_CLK			30
+
+#define IMX_DC0_LPCG_CLK_END				31
+
 #endif /* __DT_BINDINGS_CLOCK_IMX_H */