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[3/6] dt-bindings: interrupt-controller: Add binding for the Microsemi Jaguar2 interrupt controller

Message ID 20201105171535.923570-4-gregory.clement@bootlin.com
State New
Headers show
Series Extend irqchip ocelot driver to support other SoCs | expand

Commit Message

Gregory CLEMENT Nov. 5, 2020, 5:15 p.m. UTC 
Add the Device Tree binding documentation for the Microsemi Jaguar2
interrupt controller that is part of the ICPU. It is connected directly to
the MIPS core interrupt controller.

Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
---
 .../interrupt-controller/mscc,ocelot-icpu-intr.txt         | 7 ++++---
 1 file changed, 4 insertions(+), 3 deletions(-)
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Patch

diff --git a/Documentation/devicetree/bindings/interrupt-controller/mscc,ocelot-icpu-intr.txt b/Documentation/devicetree/bindings/interrupt-controller/mscc,ocelot-icpu-intr.txt
index 42de86e023a6..916832064d64 100644
--- a/Documentation/devicetree/bindings/interrupt-controller/mscc,ocelot-icpu-intr.txt
+++ b/Documentation/devicetree/bindings/interrupt-controller/mscc,ocelot-icpu-intr.txt
@@ -1,11 +1,12 @@ 
 Microsemi Ocelot SoC ICPU Interrupt Controller
 
-Luton and Servals belong the same family as Ocelot: the VCoreIII family
+Luton, Servals and Jaguar 2 belong the same family as Ocelot: the
+VCoreIII family
 
 Required properties:
 
-- compatible : should be "mscc,ocelot-icpu-intr" or "mscc,luton-icpu-intr"
-               or "mscc,serval-icpu-intr"
+- compatible : should be "mscc,ocelot-icpu-intr", "mscc,luton-icpu-intr",
+               "mscc,serval-icpu-intr" or "mscc,jaguar2-icpu-intr"
 - reg : Specifies base physical address and size of the registers.
 - interrupt-controller : Identifies the node as an interrupt controller
 - #interrupt-cells : Specifies the number of cells needed to encode an