| Message ID | 1604626378-152352-2-git-send-email-komlodi@xilinx.com |
|---|---|
| State | New |
| Headers | show |
| Series | hw/block/m25p80: Numonyx: Fix dummy cycles and check for SPI mode on cmds | expand |
On 11/6/20 2:32 AM, Joe Komlodi wrote: > QIO and DIO modes should be enabled when the bits in NVCFG are set to 0. > This matches the behavior of the other bits in the NVCFG register. Is this material for the 5.2 release? > > Signed-off-by: Joe Komlodi <komlodi@xilinx.com> > --- > hw/block/m25p80.c | 4 ++-- > 1 file changed, 2 insertions(+), 2 deletions(-) > > diff --git a/hw/block/m25p80.c b/hw/block/m25p80.c > index 483925f..4255a6a 100644 > --- a/hw/block/m25p80.c > +++ b/hw/block/m25p80.c > @@ -783,10 +783,10 @@ static void reset_memory(Flash *s) > s->enh_volatile_cfg |= EVCFG_OUT_DRIVER_STRENGTH_DEF; > s->enh_volatile_cfg |= EVCFG_VPP_ACCELERATOR; > s->enh_volatile_cfg |= EVCFG_RESET_HOLD_ENABLED; > - if (s->nonvolatile_cfg & NVCFG_DUAL_IO_MASK) { > + if (!(s->nonvolatile_cfg & NVCFG_DUAL_IO_MASK)) { > s->enh_volatile_cfg |= EVCFG_DUAL_IO_ENABLED; > } > - if (s->nonvolatile_cfg & NVCFG_QUAD_IO_MASK) { > + if (!(s->nonvolatile_cfg & NVCFG_QUAD_IO_MASK)) { > s->enh_volatile_cfg |= EVCFG_QUAD_IO_ENABLED; > } > if (!(s->nonvolatile_cfg & NVCFG_4BYTE_ADDR_MASK)) { >
Hi Philippe, -----Original Message----- From: Philippe Mathieu-Daudé <philmd@redhat.com> Sent: Monday, November 9, 2020 6:21 AM To: Joe Komlodi <komlodi@xilinx.com>; qemu-devel@nongnu.org; Cédric Le Goater <clg@kaod.org>; Edgar Iglesias <edgari@xilinx.com> Cc: Francisco Eduardo Iglesias <figlesia@xilinx.com>; alistair@alistair23.me; philippe.mathieu.daude@gmail.com; qemu-block@nongnu.org; mreitz@redhat.com Subject: Re: [PATCH v3 1/3] hw/block/m25p80: Fix Numonyx NVCFG DIO and QIO bit polarity On 11/6/20 2:32 AM, Joe Komlodi wrote: > QIO and DIO modes should be enabled when the bits in NVCFG are set to 0. > This matches the behavior of the other bits in the NVCFG register. Is this material for the 5.2 release? [Joe] If possible, yeah. Otherwise if it's too late for 5.2 I have no problems pushing it to a later release. Thanks! Joe > > Signed-off-by: Joe Komlodi <komlodi@xilinx.com> > --- > hw/block/m25p80.c | 4 ++-- > 1 file changed, 2 insertions(+), 2 deletions(-) > > diff --git a/hw/block/m25p80.c b/hw/block/m25p80.c index > 483925f..4255a6a 100644 > --- a/hw/block/m25p80.c > +++ b/hw/block/m25p80.c > @@ -783,10 +783,10 @@ static void reset_memory(Flash *s) > s->enh_volatile_cfg |= EVCFG_OUT_DRIVER_STRENGTH_DEF; > s->enh_volatile_cfg |= EVCFG_VPP_ACCELERATOR; > s->enh_volatile_cfg |= EVCFG_RESET_HOLD_ENABLED; > - if (s->nonvolatile_cfg & NVCFG_DUAL_IO_MASK) { > + if (!(s->nonvolatile_cfg & NVCFG_DUAL_IO_MASK)) { > s->enh_volatile_cfg |= EVCFG_DUAL_IO_ENABLED; > } > - if (s->nonvolatile_cfg & NVCFG_QUAD_IO_MASK) { > + if (!(s->nonvolatile_cfg & NVCFG_QUAD_IO_MASK)) { > s->enh_volatile_cfg |= EVCFG_QUAD_IO_ENABLED; > } > if (!(s->nonvolatile_cfg & NVCFG_4BYTE_ADDR_MASK)) { >
Hi Joe, On Thu, Nov 05, 2020 at 05:32:56PM -0800, Joe Komlodi wrote: > QIO and DIO modes should be enabled when the bits in NVCFG are set to 0. > This matches the behavior of the other bits in the NVCFG register. The enhanced register has the bits with the same polarities, meaning that the value should be propagated as it was before (0 - enabled and 1 - disabled). I do see though that the define naming is not perfect and can make you believe otherwise. Best regards, Francisco Iglesias > > Signed-off-by: Joe Komlodi <komlodi@xilinx.com> > --- > hw/block/m25p80.c | 4 ++-- > 1 file changed, 2 insertions(+), 2 deletions(-) > > diff --git a/hw/block/m25p80.c b/hw/block/m25p80.c > index 483925f..4255a6a 100644 > --- a/hw/block/m25p80.c > +++ b/hw/block/m25p80.c > @@ -783,10 +783,10 @@ static void reset_memory(Flash *s) > s->enh_volatile_cfg |= EVCFG_OUT_DRIVER_STRENGTH_DEF; > s->enh_volatile_cfg |= EVCFG_VPP_ACCELERATOR; > s->enh_volatile_cfg |= EVCFG_RESET_HOLD_ENABLED; > - if (s->nonvolatile_cfg & NVCFG_DUAL_IO_MASK) { > + if (!(s->nonvolatile_cfg & NVCFG_DUAL_IO_MASK)) { > s->enh_volatile_cfg |= EVCFG_DUAL_IO_ENABLED; > } > - if (s->nonvolatile_cfg & NVCFG_QUAD_IO_MASK) { > + if (!(s->nonvolatile_cfg & NVCFG_QUAD_IO_MASK)) { > s->enh_volatile_cfg |= EVCFG_QUAD_IO_ENABLED; > } > if (!(s->nonvolatile_cfg & NVCFG_4BYTE_ADDR_MASK)) { > -- > 2.7.4 >
Hi Francisco, -----Original Message----- From: Francisco Iglesias <francisco.iglesias@xilinx.com> Sent: Wednesday, November 11, 2020 6:33 AM To: Joe Komlodi <komlodi@xilinx.com> Cc: qemu-devel@nongnu.org; philippe.mathieu.daude@gmail.com; Francisco Eduardo Iglesias <figlesia@xilinx.com>; alistair@alistair23.me; qemu-block@nongnu.org; mreitz@redhat.com Subject: Re: [PATCH v3 1/3] hw/block/m25p80: Fix Numonyx NVCFG DIO and QIO bit polarity Hi Joe, On Thu, Nov 05, 2020 at 05:32:56PM -0800, Joe Komlodi wrote: > QIO and DIO modes should be enabled when the bits in NVCFG are set to 0. > This matches the behavior of the other bits in the NVCFG register. The enhanced register has the bits with the same polarities, meaning that the value should be propagated as it was before (0 - enabled and 1 - disabled). I do see though that the define naming is not perfect and can make you believe otherwise. [Joe] Ah, you're right. I'll fix that and change the bit checks in the other patches accordingly. I'll probably also add a patch to this series to change the define names to make them more accurate. Thanks! Joe Best regards, Francisco Iglesias > > Signed-off-by: Joe Komlodi <komlodi@xilinx.com> > --- > hw/block/m25p80.c | 4 ++-- > 1 file changed, 2 insertions(+), 2 deletions(-) > > diff --git a/hw/block/m25p80.c b/hw/block/m25p80.c index > 483925f..4255a6a 100644 > --- a/hw/block/m25p80.c > +++ b/hw/block/m25p80.c > @@ -783,10 +783,10 @@ static void reset_memory(Flash *s) > s->enh_volatile_cfg |= EVCFG_OUT_DRIVER_STRENGTH_DEF; > s->enh_volatile_cfg |= EVCFG_VPP_ACCELERATOR; > s->enh_volatile_cfg |= EVCFG_RESET_HOLD_ENABLED; > - if (s->nonvolatile_cfg & NVCFG_DUAL_IO_MASK) { > + if (!(s->nonvolatile_cfg & NVCFG_DUAL_IO_MASK)) { > s->enh_volatile_cfg |= EVCFG_DUAL_IO_ENABLED; > } > - if (s->nonvolatile_cfg & NVCFG_QUAD_IO_MASK) { > + if (!(s->nonvolatile_cfg & NVCFG_QUAD_IO_MASK)) { > s->enh_volatile_cfg |= EVCFG_QUAD_IO_ENABLED; > } > if (!(s->nonvolatile_cfg & NVCFG_4BYTE_ADDR_MASK)) { > -- > 2.7.4 >
diff --git a/hw/block/m25p80.c b/hw/block/m25p80.c index 483925f..4255a6a 100644 --- a/hw/block/m25p80.c +++ b/hw/block/m25p80.c @@ -783,10 +783,10 @@ static void reset_memory(Flash *s) s->enh_volatile_cfg |= EVCFG_OUT_DRIVER_STRENGTH_DEF; s->enh_volatile_cfg |= EVCFG_VPP_ACCELERATOR; s->enh_volatile_cfg |= EVCFG_RESET_HOLD_ENABLED; - if (s->nonvolatile_cfg & NVCFG_DUAL_IO_MASK) { + if (!(s->nonvolatile_cfg & NVCFG_DUAL_IO_MASK)) { s->enh_volatile_cfg |= EVCFG_DUAL_IO_ENABLED; } - if (s->nonvolatile_cfg & NVCFG_QUAD_IO_MASK) { + if (!(s->nonvolatile_cfg & NVCFG_QUAD_IO_MASK)) { s->enh_volatile_cfg |= EVCFG_QUAD_IO_ENABLED; } if (!(s->nonvolatile_cfg & NVCFG_4BYTE_ADDR_MASK)) {
QIO and DIO modes should be enabled when the bits in NVCFG are set to 0. This matches the behavior of the other bits in the NVCFG register. Signed-off-by: Joe Komlodi <komlodi@xilinx.com> --- hw/block/m25p80.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-)