| Message ID | 20201104164923.21238-13-digetx@gmail.com |
|---|---|
| State | Accepted |
| Commit | cac2a3552c9ef3ee2ff9ec72794e1ab0a1f64012 |
| Headers | show |
| Series | Introduce memory interconnect for NVIDIA Tegra SoCs | expand |
diff --git a/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra124-emc.yaml b/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra124-emc.yaml index 278549f9e051..8ae3dae42d6e 100644 --- a/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra124-emc.yaml +++ b/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra124-emc.yaml @@ -345,6 +345,7 @@ examples: #iommu-cells = <1>; #reset-cells = <1>; + #interconnect-cells = <1>; }; external-memory-controller@7001b000 { diff --git a/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra124-mc.yaml b/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra124-mc.yaml index 84d0339505b1..7b18b4d11e0a 100644 --- a/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra124-mc.yaml +++ b/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra124-mc.yaml @@ -40,6 +40,9 @@ properties: "#iommu-cells": const: 1 + "#interconnect-cells": + const: 1 + patternProperties: "^emc-timings-[0-9]+$": type: object @@ -104,6 +107,7 @@ required: - clock-names - "#reset-cells" - "#iommu-cells" + - "#interconnect-cells" additionalProperties: false @@ -119,6 +123,7 @@ examples: #iommu-cells = <1>; #reset-cells = <1>; + #interconnect-cells = <1>; emc-timings-3 { nvidia,ram-code = <3>;
Memory controller is interconnected with memory clients and with the External Memory Controller. Document new interconnect property which turns memory controller into interconnect provider. Signed-off-by: Dmitry Osipenko <digetx@gmail.com> --- .../bindings/memory-controllers/nvidia,tegra124-emc.yaml | 1 + .../bindings/memory-controllers/nvidia,tegra124-mc.yaml | 5 +++++ 2 files changed, 6 insertions(+)