@@ -13,7 +13,13 @@ Documentation/devicetree/bindings/mtd/nand.txt
Required properties:
+ - compatible: "ti,omap2-nand"
- reg: The CS line the peripheral is connected to
+ Should contain 2 resource specifiers
+ - range id (CS number), base offset and length of the
+ NAND I/O space
+ - range id, base offset and length of the GPMC register space.
+ - interrupts: Interrupt resource specifier for GPMC interrupt.
Optional properties:
@@ -53,17 +59,21 @@ Example for an AM33xx board:
gpmc: gpmc@50000000 {
compatible = "ti,am3352-gpmc";
ti,hwmods = "gpmc";
- reg = <0x50000000 0x1000000>;
+ reg = <0x50000000 0x36c>;
interrupts = <100>;
gpmc,num-cs = <8>;
gpmc,num-waitpins = <2>;
#address-cells = <2>;
#size-cells = <1>;
- ranges = <0 0 0x08000000 0x2000>; /* CS0: NAND */
+ ranges = <0 0 0x08000000 0x1000000 /* CS0 space, 16MB */
+ 255 0 0x50000000 0x36c>; /* GPMC reg space */
elm_id = <&elm>;
nand@0,0 {
- reg = <0 0 0>; /* CS0, offset 0 */
+ compatible = "ti,omap2-nand";
+ reg = <0 0 4 /* CS0, offset 0, NAND I/O window 4 */
+ 255 0 0x36c>; /* GPMC reg space */
+ interrupts = <100>;
nand-bus-width = <16>;
ti,nand-ecc-opt = "bch8";
ti,nand-xfer-type = "polled";
Add compatible id, interrupts and update reg property description. As the NAND controller needs access to GPMC register space, we need to pass a second memory resource to the NAND controller node. Due to the wierd way the reg property has been implemented (i.e. CS number required in 1st number of reg property) we will need to use a number outside the possible CS numbers for the GPMC register space. As a SoC can have fewer than 10 chip selects, 255 seems like a safe bet for the GPMC register space. Signed-off-by: Roger Quadros <rogerq@ti.com> --- Documentation/devicetree/bindings/mtd/gpmc-nand.txt | 16 +++++++++++++--- 1 file changed, 13 insertions(+), 3 deletions(-)