| Message ID | 1400777250-17335-15-git-send-email-will.deacon@arm.com |
|---|---|
| State | New |
| Headers | show |
On Thu, May 22, 2014 at 05:47:26PM +0100, Will Deacon wrote: > write{b,w,l,q}_relaxed are implemented by some architectures in order to > permit memory-mapped I/O accesses with weaker barrier semantics than the > non-relaxed variants. > > This patch adds dummy macros for the write accessors to sparc, in the > same vein as the dummy definitions for the relaxed read accessors. The > existing relaxed read{b,w,l} accessors are moved into asm/io.h, since > they are identical between 32-bit and 64-bit machines. > > Cc: "David S. Miller" <davem@davemloft.net> > Signed-off-by: Will Deacon <will.deacon@arm.com> Look good: Acked-by: Sam Ravnborg <sam@ravnborg.org> But you should wait for David's ack too. Sam -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
On Thu, May 22, 2014 at 07:18:38PM +0100, Sam Ravnborg wrote: > On Thu, May 22, 2014 at 05:47:26PM +0100, Will Deacon wrote: > > write{b,w,l,q}_relaxed are implemented by some architectures in order to > > permit memory-mapped I/O accesses with weaker barrier semantics than the > > non-relaxed variants. > > > > This patch adds dummy macros for the write accessors to sparc, in the > > same vein as the dummy definitions for the relaxed read accessors. The > > existing relaxed read{b,w,l} accessors are moved into asm/io.h, since > > they are identical between 32-bit and 64-bit machines. > > > > Cc: "David S. Miller" <davem@davemloft.net> > > Signed-off-by: Will Deacon <will.deacon@arm.com> > Look good: > Acked-by: Sam Ravnborg <sam@ravnborg.org> Thanks, Sam. > But you should wait for David's ack too. Yeah, I still need to get buy-in on the semantics from the PPC folks anyway. Will -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
From: Will Deacon <will.deacon@arm.com> Date: Fri, 23 May 2014 15:38:10 +0100 > On Thu, May 22, 2014 at 07:18:38PM +0100, Sam Ravnborg wrote: >> On Thu, May 22, 2014 at 05:47:26PM +0100, Will Deacon wrote: >> > write{b,w,l,q}_relaxed are implemented by some architectures in order to >> > permit memory-mapped I/O accesses with weaker barrier semantics than the >> > non-relaxed variants. >> > >> > This patch adds dummy macros for the write accessors to sparc, in the >> > same vein as the dummy definitions for the relaxed read accessors. The >> > existing relaxed read{b,w,l} accessors are moved into asm/io.h, since >> > they are identical between 32-bit and 64-bit machines. >> > >> > Cc: "David S. Miller" <davem@davemloft.net> >> > Signed-off-by: Will Deacon <will.deacon@arm.com> >> Look good: >> Acked-by: Sam Ravnborg <sam@ravnborg.org> > > Thanks, Sam. > >> But you should wait for David's ack too. > > Yeah, I still need to get buy-in on the semantics from the PPC folks > anyway. I'm fine with these changes so: Acked-by: David S. Miller <davem@davemloft.net> Unfortunately, whilst sparc64 could support the relaxed variants, there is no easy way to implement this. I/O addrs are simply physical addresses on sparc64, and we therefore do loads and stores via the ASY_PHYS_BYPASS_EC_E* address spaces. What this address space means is "physical address", "bypass caches", "side effect". To do a relaxed variant we'd need something without the "side effect" part, but no such ASI exists. These are all page protection bits, so we could move to using virtual mappings on I/O things, but that's so much overkill just for this I think. Besides there are bigger fish to fry on sparc64 :-) -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
diff --git a/arch/sparc/include/asm/io.h b/arch/sparc/include/asm/io.h index f6902cf3cbe9..493f22c4684f 100644 --- a/arch/sparc/include/asm/io.h +++ b/arch/sparc/include/asm/io.h @@ -10,6 +10,15 @@ * Defines used for both SPARC32 and SPARC64 */ +/* Relaxed accessors for MMIO */ +#define readb_relaxed(__addr) readb(__addr) +#define readw_relaxed(__addr) readw(__addr) +#define readl_relaxed(__addr) readl(__addr) + +#define writeb_relaxed(__b, __addr) writeb(__b, __addr) +#define writew_relaxed(__w, __addr) writew(__w, __addr) +#define writel_relaxed(__l, __addr) writel(__l, __addr) + /* Big endian versions of memory read/write routines */ #define readb_be(__addr) __raw_readb(__addr) #define readw_be(__addr) __raw_readw(__addr) diff --git a/arch/sparc/include/asm/io_32.h b/arch/sparc/include/asm/io_32.h index c1acbd891cbc..41d33e567f1d 100644 --- a/arch/sparc/include/asm/io_32.h +++ b/arch/sparc/include/asm/io_32.h @@ -89,9 +89,6 @@ static inline void __writel(u32 l, volatile void __iomem *addr) #define readb(__addr) __readb(__addr) #define readw(__addr) __readw(__addr) #define readl(__addr) __readl(__addr) -#define readb_relaxed(__addr) readb(__addr) -#define readw_relaxed(__addr) readw(__addr) -#define readl_relaxed(__addr) readl(__addr) #define writeb(__b, __addr) __writeb((__b),(__addr)) #define writew(__w, __addr) __writew((__w),(__addr)) diff --git a/arch/sparc/include/asm/io_64.h b/arch/sparc/include/asm/io_64.h index 09b0b88aeb2a..2b4cd52831d0 100644 --- a/arch/sparc/include/asm/io_64.h +++ b/arch/sparc/include/asm/io_64.h @@ -203,18 +203,16 @@ static inline void _writeq(u64 q, volatile void __iomem *addr) : "memory"); } -#define readb(__addr) _readb(__addr) -#define readw(__addr) _readw(__addr) -#define readl(__addr) _readl(__addr) -#define readq(__addr) _readq(__addr) -#define readb_relaxed(__addr) _readb(__addr) -#define readw_relaxed(__addr) _readw(__addr) -#define readl_relaxed(__addr) _readl(__addr) -#define readq_relaxed(__addr) _readq(__addr) -#define writeb(__b, __addr) _writeb(__b, __addr) -#define writew(__w, __addr) _writew(__w, __addr) -#define writel(__l, __addr) _writel(__l, __addr) -#define writeq(__q, __addr) _writeq(__q, __addr) +#define readb(__addr) _readb(__addr) +#define readw(__addr) _readw(__addr) +#define readl(__addr) _readl(__addr) +#define readq(__addr) _readq(__addr) +#define readq_relaxed(__addr) _readq(__addr) +#define writeb(__b, __addr) _writeb(__b, __addr) +#define writew(__w, __addr) _writew(__w, __addr) +#define writel(__l, __addr) _writel(__l, __addr) +#define writeq(__q, __addr) _writeq(__q, __addr) +#define writeq_relaxed(__q, __addr) _writeq(__q, __addr) /* Now versions without byte-swapping. */ static inline u8 _raw_readb(unsigned long addr)
write{b,w,l,q}_relaxed are implemented by some architectures in order to permit memory-mapped I/O accesses with weaker barrier semantics than the non-relaxed variants. This patch adds dummy macros for the write accessors to sparc, in the same vein as the dummy definitions for the relaxed read accessors. The existing relaxed read{b,w,l} accessors are moved into asm/io.h, since they are identical between 32-bit and 64-bit machines. Cc: "David S. Miller" <davem@davemloft.net> Signed-off-by: Will Deacon <will.deacon@arm.com> --- arch/sparc/include/asm/io.h | 9 +++++++++ arch/sparc/include/asm/io_32.h | 3 --- arch/sparc/include/asm/io_64.h | 22 ++++++++++------------ 3 files changed, 19 insertions(+), 15 deletions(-)