diff mbox series

[RFC,13/14] alpha/: fix some comment spelling errors

Message ID 20200930095321.2006-14-zhaolichang@huawei.com
State New
Headers show
Series fix some comment spelling errors | expand

Commit Message

Lichang Zhao Sept. 30, 2020, 9:53 a.m. UTC
I found that there are many spelling errors in the comments of qemu/target/alpha.
I used spellcheck to check the spelling errors and found some errors in the folder.

Signed-off-by: zhaolichang <zhaolichang@huawei.com>
---
 target/alpha/cpu.h       | 4 ++--
 target/alpha/translate.c | 2 +-
 2 files changed, 3 insertions(+), 3 deletions(-)

Comments

David Edmondson Sept. 30, 2020, 10:56 a.m. UTC | #1
On Wednesday, 2020-09-30 at 17:53:20 +08, zhaolichang wrote:

> I found that there are many spelling errors in the comments of qemu/target/alpha.

> I used spellcheck to check the spelling errors and found some errors in the folder.

>

> Signed-off-by: zhaolichang <zhaolichang@huawei.com>


Reviewed-by: David Edmondson <david.edmondson@oracle.com>


> ---

>  target/alpha/cpu.h       | 4 ++--

>  target/alpha/translate.c | 2 +-

>  2 files changed, 3 insertions(+), 3 deletions(-)

>

> diff --git a/target/alpha/cpu.h b/target/alpha/cpu.h

> index be29bdd..8a6d477 100644

> --- a/target/alpha/cpu.h

> +++ b/target/alpha/cpu.h

> @@ -190,7 +190,7 @@ enum {

>  

>     That said, we're only emulating Unix PALcode, and not attempting VMS,

>     so we don't need to implement Executive and Supervisor.  QEMU's own

> -   PALcode cheats and usees the KSEG mapping for its code+data rather than

> +   PALcode cheats and uses the KSEG mapping for its code+data rather than

>     physical addresses.  */

>  

>  #define MMU_KERNEL_IDX   0

> @@ -370,7 +370,7 @@ enum {

>     The Unix PALcode only uses bit 4.  */

>  #define PS_USER_MODE  8u

>  

> -/* CPUAlphaState->flags constants.  These are layed out so that we

> +/* CPUAlphaState->flags constants.  These are laid out so that we

>     can set or reset the pieces individually by assigning to the byte,

>     or manipulated as a whole.  */

>  

> diff --git a/target/alpha/translate.c b/target/alpha/translate.c

> index 8870284..6aef9ec 100644

> --- a/target/alpha/translate.c

> +++ b/target/alpha/translate.c

> @@ -2939,7 +2939,7 @@ static void alpha_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cpu)

>         the first fp insn of the TB.  Alternately we could define a proper

>         default for every TB (e.g. QUAL_RM_N or QUAL_RM_D) and make sure

>         to reset the FP_STATUS to that default at the end of any TB that

> -       changes the default.  We could even (gasp) dynamiclly figure out

> +       changes the default.  We could even (gasp) dynamically figure out

>         what default would be most efficient given the running program.  */

>      ctx->tb_rm = -1;

>      /* Similarly for flush-to-zero.  */

> -- 

> 2.26.2.windows.1


dme.
-- 
They like the smell of it in Hollywood.
Philippe Mathieu-Daudé Sept. 30, 2020, 4:01 p.m. UTC | #2
On 9/30/20 11:53 AM, zhaolichang wrote:
> I found that there are many spelling errors in the comments of qemu/target/alpha.

> I used spellcheck to check the spelling errors and found some errors in the folder.

> 

> Signed-off-by: zhaolichang <zhaolichang@huawei.com>

> ---

>  target/alpha/cpu.h       | 4 ++--

>  target/alpha/translate.c | 2 +-

>  2 files changed, 3 insertions(+), 3 deletions(-)


Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
diff mbox series

Patch

diff --git a/target/alpha/cpu.h b/target/alpha/cpu.h
index be29bdd..8a6d477 100644
--- a/target/alpha/cpu.h
+++ b/target/alpha/cpu.h
@@ -190,7 +190,7 @@  enum {
 
    That said, we're only emulating Unix PALcode, and not attempting VMS,
    so we don't need to implement Executive and Supervisor.  QEMU's own
-   PALcode cheats and usees the KSEG mapping for its code+data rather than
+   PALcode cheats and uses the KSEG mapping for its code+data rather than
    physical addresses.  */
 
 #define MMU_KERNEL_IDX   0
@@ -370,7 +370,7 @@  enum {
    The Unix PALcode only uses bit 4.  */
 #define PS_USER_MODE  8u
 
-/* CPUAlphaState->flags constants.  These are layed out so that we
+/* CPUAlphaState->flags constants.  These are laid out so that we
    can set or reset the pieces individually by assigning to the byte,
    or manipulated as a whole.  */
 
diff --git a/target/alpha/translate.c b/target/alpha/translate.c
index 8870284..6aef9ec 100644
--- a/target/alpha/translate.c
+++ b/target/alpha/translate.c
@@ -2939,7 +2939,7 @@  static void alpha_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cpu)
        the first fp insn of the TB.  Alternately we could define a proper
        default for every TB (e.g. QUAL_RM_N or QUAL_RM_D) and make sure
        to reset the FP_STATUS to that default at the end of any TB that
-       changes the default.  We could even (gasp) dynamiclly figure out
+       changes the default.  We could even (gasp) dynamically figure out
        what default would be most efficient given the running program.  */
     ctx->tb_rm = -1;
     /* Similarly for flush-to-zero.  */