| Message ID | 29a8c766c7c4748d0f2711c3a0abb81208138c5e.1601652179.git.alistair.francis@wdc.com |
|---|---|
| State | New |
| Headers | show |
| Series | [v2,1/1] riscv: Convert interrupt logs to use qemu_log_mask() | expand |
On Fri, Oct 2, 2020 at 8:35 AM Alistair Francis <alistair.francis@wdc.com> wrote: > > Currently we log interrupts and exceptions using the trace backend in > riscv_cpu_do_interrupt(). We also log exceptions using the interrupt log > mask (-d int) in riscv_raise_exception(). > > This patch converts riscv_cpu_do_interrupt() to log both interrupts and > exceptions with the interrupt log mask, so that both are printed when a > user runs QEMU with -d int. > > Signed-off-by: Alistair Francis <alistair.francis@wdc.com> > Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Thanks! Applied to riscv-to-apply.next Alistair > --- > target/riscv/cpu_helper.c | 8 +++++++- > target/riscv/op_helper.c | 1 - > 2 files changed, 7 insertions(+), 2 deletions(-) > > diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c > index 904899054d..6c68239a46 100644 > --- a/target/riscv/cpu_helper.c > +++ b/target/riscv/cpu_helper.c > @@ -895,7 +895,13 @@ void riscv_cpu_do_interrupt(CPUState *cs) > } > > trace_riscv_trap(env->mhartid, async, cause, env->pc, tval, > - riscv_cpu_get_trap_name(cause, async)); > + riscv_cpu_get_trap_name(cause, async)); > + > + qemu_log_mask(CPU_LOG_INT, > + "%s: hart:"TARGET_FMT_ld", async:%d, cause:"TARGET_FMT_lx", " > + "epc:0x"TARGET_FMT_lx", tval:0x"TARGET_FMT_lx", desc=%s\n", > + __func__, env->mhartid, async, cause, env->pc, tval, > + riscv_cpu_get_trap_name(cause, async)); > > if (env->priv <= PRV_S && > cause < TARGET_LONG_BITS && ((deleg >> cause) & 1)) { > diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c > index 9b9ada45a9..e987bd262f 100644 > --- a/target/riscv/op_helper.c > +++ b/target/riscv/op_helper.c > @@ -29,7 +29,6 @@ void QEMU_NORETURN riscv_raise_exception(CPURISCVState *env, > uint32_t exception, uintptr_t pc) > { > CPUState *cs = env_cpu(env); > - qemu_log_mask(CPU_LOG_INT, "%s: %d\n", __func__, exception); > cs->exception_index = exception; > cpu_loop_exit_restore(cs, pc); > } > -- > 2.28.0 >
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index 904899054d..6c68239a46 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -895,7 +895,13 @@ void riscv_cpu_do_interrupt(CPUState *cs) } trace_riscv_trap(env->mhartid, async, cause, env->pc, tval, - riscv_cpu_get_trap_name(cause, async)); + riscv_cpu_get_trap_name(cause, async)); + + qemu_log_mask(CPU_LOG_INT, + "%s: hart:"TARGET_FMT_ld", async:%d, cause:"TARGET_FMT_lx", " + "epc:0x"TARGET_FMT_lx", tval:0x"TARGET_FMT_lx", desc=%s\n", + __func__, env->mhartid, async, cause, env->pc, tval, + riscv_cpu_get_trap_name(cause, async)); if (env->priv <= PRV_S && cause < TARGET_LONG_BITS && ((deleg >> cause) & 1)) { diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c index 9b9ada45a9..e987bd262f 100644 --- a/target/riscv/op_helper.c +++ b/target/riscv/op_helper.c @@ -29,7 +29,6 @@ void QEMU_NORETURN riscv_raise_exception(CPURISCVState *env, uint32_t exception, uintptr_t pc) { CPUState *cs = env_cpu(env); - qemu_log_mask(CPU_LOG_INT, "%s: %d\n", __func__, exception); cs->exception_index = exception; cpu_loop_exit_restore(cs, pc); }