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[PULL,39/44] docs/system: Update MIPS CPU documentation

Message ID	20201017140243.1078718-40-f4bug@amsat.org
State	New
Headers	show Return-Path: <SRS0=yvcL=DY=nongnu.org=qemu-devel-bounces+qemu-devel=archiver.kernel.org@kernel.org> DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 99BE920714 From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= <f4bug@amsat.org> To: qemu-devel@nongnu.org Subject: [PULL 39/44] docs/system: Update MIPS CPU documentation Date: Sat, 17 Oct 2020 16:02:38 +0200 Message-Id: <20201017140243.1078718-40-f4bug@amsat.org> In-Reply-To: <20201017140243.1078718-1-f4bug@amsat.org> References: <20201017140243.1078718-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::434; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wr1-x434.google.com Precedence: list Cc: Huacai Chen <zltjiangshi@gmail.com>, Aleksandar Rikalo <aleksandar.rikalo@syrmia.com>, Paul Burton <paulburton@kernel.org>, =?utf-8?q?Philippe_Mathieu-Daud?= =?utf-8?b?w6k=?= <f4bug@amsat.org>, =?utf-8?q?Herv=C3=A9_Poussineau?= <hpoussin@reactos.org>, Huacai Chen <chenhc@lemote.com>, Aurelien Jarno <aurelien@aurel32.net> Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" <qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org>
Series	mips-next patches for 2020-10-17 \| expand [PULL,00/44] mips-next patches for 2020-10-17 [PULL,01/44] util/cutils: Introduce freq_to_str() to display Hertz units [PULL,02/44] hw/qdev-clock: Display error hint when clock is missing from device [PULL,03/44] hw/core/clock: Add the clock_new helper function [PULL,04/44] target/mips: Fix some comment spelling errors [PULL,05/44] target/mips: Demacro helpers for <ABS\|CHS>.<D\|S\|PS> [PULL,06/44] target/mips: Demacro helpers for M<ADD\|SUB>F.<D\|S> [PULL,07/44] target/mips: Demacro helpers for <MAX\|MAXA\|MIN\|MINA>.<D\|S> [PULL,08/44] target/mips: Add loongson-ext lswc2 group of instructions (Part 1) [PULL,09/44] target/mips: Add loongson-ext lswc2 group of instructions (Part 2) [PULL,10/44] target/mips: Add loongson-ext lsdc2 group of instructions [PULL,11/44] target/mips/op_helper: Convert multiple if() to switch case [PULL,12/44] target/mips/op_helper: Document Invalidate/Writeback opcodes as no-op [PULL,13/44] target/mips/op_helper: Log unimplemented cache opcode [PULL,14/44] target/mips: Move cpu_mips_get_random() with CP0 helpers [PULL,15/44] target/mips/cp0_timer: Explicit unit in variable name [PULL,16/44] target/mips/cp0_timer: Document TIMER_PERIOD origin [PULL,17/44] target/mips: Move cp0_count_ns to CPUMIPSState [PULL,18/44] target/mips/cpu: Calculate the CP0 timer period using the CPU frequency [PULL,19/44] target/mips/cpu: Make cp0_count_rate a property [PULL,20/44] target/mips/cpu: Allow the CPU to use dynamic frequencies [PULL,21/44] target/mips/cpu: Introduce mips_cpu_create_with_clock() helper [PULL,22/44] hw/mips/r4k: Explicit CPU frequency is 200 MHz [PULL,23/44] hw/mips/fuloong2e: Set CPU frequency to 533 MHz [PULL,24/44] hw/mips/mipssim: Correct CPU frequency [PULL,25/44] hw/mips/jazz: Correct CPU frequencies [PULL,26/44] hw/mips/cps: Expose input clock and connect it to CPU cores [PULL,27/44] hw/mips/boston: Set CPU frequency to 1 GHz [PULL,28/44] hw/mips/malta: Set CPU frequency to 320 MHz [PULL,29/44] hw/mips/cps: Do not allow use without input clock [PULL,30/44] target/mips/cpu: Display warning when CPU is used without input clock [PULL,31/44] hw/mips/malta: Fix FPGA I/O region size [PULL,32/44] hw/mips/malta: Move gt64120 related code together [PULL,33/44] hw/mips/malta: Use clearer qdev style [PULL,34/44] hw/mips: Simplify loading 64-bit ELF kernels [PULL,35/44] hw/mips: Simplify code using ROUND_UP(INITRD_PAGE_SIZE) [PULL,36/44] hw/mips: Rename TYPE_MIPS_BOSTON to TYPE_BOSTON [PULL,37/44] hw/mips: Remove exit(1) in case of missing ROM [PULL,38/44] tests/acceptance: Add MIPS record/replay tests [PULL,39/44] docs/system: Update MIPS CPU documentation [PULL,40/44] MAINTAINERS: Remove myself [PULL,41/44] MAINTAINERS: Put myself forward for MIPS target [PULL,42/44] MAINTAINERS: Downgrade MIPS Boston to 'Odd Fixes', fix Paul Burton mail [PULL,43/44] MAINTAINERS: Remove duplicated Malta test entries [PULL,44/44] target/mips: Increase number of TLB entries on the 34Kf core (16 -> 64)

Commit Message

Philippe Mathieu-Daudé Oct. 17, 2020, 2:02 p.m. UTC

From: Huacai Chen <zltjiangshi@gmail.com>

Add Loongson-3A CPU models description.

Signed-off-by: Huacai Chen <chenhc@lemote.com>
Message-Id: <1602059975-10115-10-git-send-email-chenhc@lemote.com>
[PMD: Split patch in 2: CPU / machine]
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
 docs/system/cpu-models-mips.rst.inc | 10 ++++++++--
 1 file changed, 8 insertions(+), 2 deletions(-)

diff mbox series

Patch

diff --git a/docs/system/cpu-models-mips.rst.inc b/docs/system/cpu-models-mips.rst.inc
index 499b5b6fedb..02cc4bb884c 100644
--- a/docs/system/cpu-models-mips.rst.inc
+++ b/docs/system/cpu-models-mips.rst.inc
@@ -48,11 +48,17 @@  across all desired hosts.
 ``I6400``
     MIPS64 Processor (Release 6, 2014)
 
+``Loongson-2E``
+    MIPS64 Processor (Loongson 2, 2006)
+
 ``Loongson-2F``
     MIPS64 Processor (Loongson 2, 2008)
 
-``Loongson-2E``
-    MIPS64 Processor (Loongson 2, 2006)
+``Loongson-3A1000``
+    MIPS64 Processor (Loongson 3, 2010)
+
+``Loongson-3A4000``
+    MIPS64 Processor (Loongson 3, 2018)
 
 ``mips64dspr2``
     MIPS64 Processor (Release 2, 2006)