| Message ID | 20201023214506.917601-3-keithp@keithp.com |
|---|---|
| State | New |
| Headers | show |
| Series | riscv: Add SiFive test device to sifive targets | expand |
On Fri, Oct 23, 2020 at 2:48 PM Keith Packard via <qemu-devel@nongnu.org> wrote: > > The SiFive test device provides a mechanism for terminating the qemu > instance from the emulated system. This patch adds that device to the > sifive_u target, including constructing a suitable FDT node. > > Signed-off-by: Keith Packard <keithp@keithp.com> > --- > hw/riscv/sifive_u.c | 15 +++++++++++++++ > include/hw/riscv/sifive_u.h | 1 + > 2 files changed, 16 insertions(+) > > diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c > index 6ad975d692..8d803fe7c0 100644 > --- a/hw/riscv/sifive_u.c > +++ b/hw/riscv/sifive_u.c > @@ -15,6 +15,7 @@ > * 5) OTP (One-Time Programmable) memory with stored serial number > * 6) GEM (Gigabit Ethernet Controller) and management block > * 7) DMA (Direct Memory Access Controller) > + * 8) TEST (Test device) > * > * This board currently generates devicetree dynamically that indicates at least > * two harts and up to five harts. > @@ -44,6 +45,7 @@ > #include "hw/char/serial.h" > #include "hw/cpu/cluster.h" > #include "hw/misc/unimp.h" > +#include "hw/misc/sifive_test.h" > #include "target/riscv/cpu.h" > #include "hw/riscv/riscv_hart.h" > #include "hw/riscv/sifive_u.h" > @@ -72,6 +74,7 @@ static const struct MemmapEntry { > } sifive_u_memmap[] = { > [SIFIVE_U_DEV_DEBUG] = { 0x0, 0x100 }, > [SIFIVE_U_DEV_MROM] = { 0x1000, 0xf000 }, > + [SIFIVE_U_DEV_TEST] = { 0x100000, 0x1000 }, I also don't see this in the FU540 memory map. Alistair > [SIFIVE_U_DEV_CLINT] = { 0x2000000, 0x10000 }, > [SIFIVE_U_DEV_L2CC] = { 0x2010000, 0x1000 }, > [SIFIVE_U_DEV_PDMA] = { 0x3000000, 0x100000 }, > @@ -397,6 +400,16 @@ static void create_fdt(SiFiveUState *s, const struct MemmapEntry *memmap, > qemu_fdt_setprop_string(fdt, "/aliases", "serial0", nodename); > > g_free(nodename); > + > + nodename = g_strdup_printf("/soc/test@%lx", > + (long)memmap[SIFIVE_U_DEV_TEST].base); > + qemu_fdt_add_subnode(fdt, nodename); > + qemu_fdt_setprop_string(fdt, nodename, "compatible", "sifive,test0"); > + qemu_fdt_setprop_cells(fdt, nodename, "reg", > + 0x0, memmap[SIFIVE_U_DEV_TEST].base, > + 0x0, memmap[SIFIVE_U_DEV_TEST].size); > + > + g_free(nodename); > } > > static void sifive_u_machine_reset(void *opaque, int n, int level) > @@ -780,6 +793,8 @@ static void sifive_u_soc_realize(DeviceState *dev, Error **errp) > sysbus_connect_irq(SYS_BUS_DEVICE(&s->gem), 0, > qdev_get_gpio_in(DEVICE(s->plic), SIFIVE_U_GEM_IRQ)); > > + sifive_test_create(memmap[SIFIVE_U_DEV_TEST].base); > + > create_unimplemented_device("riscv.sifive.u.gem-mgmt", > memmap[SIFIVE_U_DEV_GEM_MGMT].base, memmap[SIFIVE_U_DEV_GEM_MGMT].size); > > diff --git a/include/hw/riscv/sifive_u.h b/include/hw/riscv/sifive_u.h > index 22e7e6efa1..4b3ebc3fc6 100644 > --- a/include/hw/riscv/sifive_u.h > +++ b/include/hw/riscv/sifive_u.h > @@ -72,6 +72,7 @@ typedef struct SiFiveUState { > enum { > SIFIVE_U_DEV_DEBUG, > SIFIVE_U_DEV_MROM, > + SIFIVE_U_DEV_TEST, > SIFIVE_U_DEV_CLINT, > SIFIVE_U_DEV_L2CC, > SIFIVE_U_DEV_PDMA, > -- > 2.28.0 > >
Alistair Francis <alistair23@gmail.com> writes:
> I also don't see this in the FU540 memory map.
Same as for the FE310 -- this is a QEMU-only device. In addition,
OpenSBI expects to use this when built for QEMU.
--
-keith
Hi Keith, On Sat, Oct 24, 2020 at 8:17 AM Keith Packard via <qemu-devel@nongnu.org> wrote: > > Alistair Francis <alistair23@gmail.com> writes: > > > I also don't see this in the FU540 memory map. > > Same as for the FE310 -- this is a QEMU-only device. In addition, > OpenSBI expects to use this when built for QEMU. I agree with Alistair. This should not be put in the sifive_u machine. For sifive_u, the hardware provides "gpio-restart" to reset the board. Regards, Bin
diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c index 6ad975d692..8d803fe7c0 100644 --- a/hw/riscv/sifive_u.c +++ b/hw/riscv/sifive_u.c @@ -15,6 +15,7 @@ * 5) OTP (One-Time Programmable) memory with stored serial number * 6) GEM (Gigabit Ethernet Controller) and management block * 7) DMA (Direct Memory Access Controller) + * 8) TEST (Test device) * * This board currently generates devicetree dynamically that indicates at least * two harts and up to five harts. @@ -44,6 +45,7 @@ #include "hw/char/serial.h" #include "hw/cpu/cluster.h" #include "hw/misc/unimp.h" +#include "hw/misc/sifive_test.h" #include "target/riscv/cpu.h" #include "hw/riscv/riscv_hart.h" #include "hw/riscv/sifive_u.h" @@ -72,6 +74,7 @@ static const struct MemmapEntry { } sifive_u_memmap[] = { [SIFIVE_U_DEV_DEBUG] = { 0x0, 0x100 }, [SIFIVE_U_DEV_MROM] = { 0x1000, 0xf000 }, + [SIFIVE_U_DEV_TEST] = { 0x100000, 0x1000 }, [SIFIVE_U_DEV_CLINT] = { 0x2000000, 0x10000 }, [SIFIVE_U_DEV_L2CC] = { 0x2010000, 0x1000 }, [SIFIVE_U_DEV_PDMA] = { 0x3000000, 0x100000 }, @@ -397,6 +400,16 @@ static void create_fdt(SiFiveUState *s, const struct MemmapEntry *memmap, qemu_fdt_setprop_string(fdt, "/aliases", "serial0", nodename); g_free(nodename); + + nodename = g_strdup_printf("/soc/test@%lx", + (long)memmap[SIFIVE_U_DEV_TEST].base); + qemu_fdt_add_subnode(fdt, nodename); + qemu_fdt_setprop_string(fdt, nodename, "compatible", "sifive,test0"); + qemu_fdt_setprop_cells(fdt, nodename, "reg", + 0x0, memmap[SIFIVE_U_DEV_TEST].base, + 0x0, memmap[SIFIVE_U_DEV_TEST].size); + + g_free(nodename); } static void sifive_u_machine_reset(void *opaque, int n, int level) @@ -780,6 +793,8 @@ static void sifive_u_soc_realize(DeviceState *dev, Error **errp) sysbus_connect_irq(SYS_BUS_DEVICE(&s->gem), 0, qdev_get_gpio_in(DEVICE(s->plic), SIFIVE_U_GEM_IRQ)); + sifive_test_create(memmap[SIFIVE_U_DEV_TEST].base); + create_unimplemented_device("riscv.sifive.u.gem-mgmt", memmap[SIFIVE_U_DEV_GEM_MGMT].base, memmap[SIFIVE_U_DEV_GEM_MGMT].size); diff --git a/include/hw/riscv/sifive_u.h b/include/hw/riscv/sifive_u.h index 22e7e6efa1..4b3ebc3fc6 100644 --- a/include/hw/riscv/sifive_u.h +++ b/include/hw/riscv/sifive_u.h @@ -72,6 +72,7 @@ typedef struct SiFiveUState { enum { SIFIVE_U_DEV_DEBUG, SIFIVE_U_DEV_MROM, + SIFIVE_U_DEV_TEST, SIFIVE_U_DEV_CLINT, SIFIVE_U_DEV_L2CC, SIFIVE_U_DEV_PDMA,
The SiFive test device provides a mechanism for terminating the qemu instance from the emulated system. This patch adds that device to the sifive_u target, including constructing a suitable FDT node. Signed-off-by: Keith Packard <keithp@keithp.com> --- hw/riscv/sifive_u.c | 15 +++++++++++++++ include/hw/riscv/sifive_u.h | 1 + 2 files changed, 16 insertions(+)