[v6,14/15] ARM: hisi: enable erratum 798181 of A15 on HiP04

Message ID	1399795571-17231-15-git-send-email-haojian.zhuang@linaro.org
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Headers	show Return-Path: <patchwork-forward+bncBCUY3LGNZALBB7XBXSNQKGQEZXSI2SY@linaro.org> Received-SPF: pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.128.171 as permitted sender) client-ip=209.85.128.171; Received-SPF: none (google.com: linux-arm-kernel-bounces+patch=linaro.org@lists.infradead.org does not designate permitted sender hosts) client-ip=2001:1868:205::9; From: Haojian Zhuang <haojian.zhuang@linaro.org> To: tglx@linutronix.de, linux@arm.linux.org.uk, linux-arm-kernel@lists.infradead.org, arnd@arndb.de, olof@lixom.net, khilman@kernel.org, xuwei5@hisilicon.com, christoffer.dall@linaro.org, Dave.Martin@arm.com, nicolas.pitre@linaro.org, marc.zyngier@arm.com Subject: [PATCH v6 14/15] ARM: hisi: enable erratum 798181 of A15 on HiP04 Date: Sun, 11 May 2014 16:06:10 +0800 Message-Id: <1399795571-17231-15-git-send-email-haojian.zhuang@linaro.org> In-Reply-To: <1399795571-17231-1-git-send-email-haojian.zhuang@linaro.org> References: <1399795571-17231-1-git-send-email-haojian.zhuang@linaro.org> summary: Content analysis details: (-0.0 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.0 RCVD_IN_DNSWL_NONE RBL: Sender listed at http://www.dnswl.org/, no trust [209.85.192.170 listed in list.dnswl.org] -0.0 SPF_PASS SPF: sender matches SPF record Cc: Kefeng Wang <kefeng.wang@linaro.org> Precedence: list MIME-Version: 1.0 Sender: "linux-arm-kernel" <linux-arm-kernel-bounces@lists.infradead.org> Errors-To: linux-arm-kernel-bounces+patch=linaro.org@lists.infradead.org Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit

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From: Haojian Zhuang <haojian.zhuang@linaro.org>
To: tglx@linutronix.de, linux@arm.linux.org.uk,
	linux-arm-kernel@lists.infradead.org, arnd@arndb.de, olof@lixom.net, 
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	Dave.Martin@arm.com, nicolas.pitre@linaro.org, marc.zyngier@arm.com
Subject: [PATCH v6 14/15] ARM: hisi: enable erratum 798181 of A15 on HiP04
Date: Sun, 11 May 2014 16:06:10 +0800
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Commit Message

Haojian Zhuang May 11, 2014, 8:06 a.m. UTC

From: Kefeng Wang <kefeng.wang@linaro.org>

The commit 93dc688 (ARM: 7684/1: errata: Workaround for Cortex-A15
erratum 798181 (TLBI/DSB operations)) introduced a workaround for
Cortex-A15 erratum 798181. Enable it for HIP04(Cortex-a15 r3p2).

Signed-off-by: Kefeng Wang <kefeng.wang@linaro.org>
Singed-off-by: Haojian Zhuang <haojian.zhuang@linaro.org>
---
 arch/arm/mach-hisi/Kconfig | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/arm/mach-hisi/Kconfig b/arch/arm/mach-hisi/Kconfig
index 3f1ece7..0a5a49d 100644
--- a/arch/arm/mach-hisi/Kconfig
+++ b/arch/arm/mach-hisi/Kconfig
@@ -21,6 +21,7 @@  config ARCH_HI3xxx
 
 config ARCH_HIP04
 	bool "Hisilicon HiP04 Cortex A15 family" if ARCH_MULTI_V7
+	select ARM_ERRATA_798181 if SMP
 	select HAVE_ARM_ARCH_TIMER
 	select MCPM if SMP
 	select MCPM_QUAD_CLUSTER if SMP

[v6,14/15] ARM: hisi: enable erratum 798181 of A15 on HiP04

Commit Message

Patch