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RFR: Optimise C2 entry point verification

Message ID 1399643484.8672.11.camel@localhost.localdomain
State New
Headers show

Commit Message

Edward Nevill May 9, 2014, 1:51 p.m. UTC 
Hi,

The following patch makes a small optimsation to the entry point verification for C2.

The patch replaces

  0x00007fc5c111ebe0: ldr       wscratch1, [x1,#8]  ;   {no_reloc}
  0x00007fc5c111ebe4: lsl       xscratch1, xscratch1, #3
  0x00007fc5c111ebe8: cmp       xscratch2, xscratch1
  0x00007fc5c111ebec: b.eq      0x00007fc5c111ebf4
  0x00007fc5c111ebf0: b 0x00007fc5c10cdb20      ;   {runtime_call}
  0x00007fc5c111ebf4: nop
  0x00007fc5c111ebf8: nop
  0x00007fc5c111ebfc: nop
[Verified Entry Point]
  ...

with the following

  0x00007f077111ebe0: ldr       wscratch1, [x1,#8]  ;   {no_reloc}
  0x00007f077111ebe4: cmp       xscratch2, xscratch1, lsl #3
  0x00007f077111ebe8: b.eq      0x00007f077111ebf0
  0x00007f077111ebec: b 0x00007f07710cdb20      ;   {runtime_call}
[Verified Entry Point]
  ...

Should we also change CodeEntryAlignment which is currently set to 32? I can see very little point in the code entry alignment being less than a cache line.

OK?
Ed.

--- CUT HERE ---
exporting patch:
# HG changeset patch
# User Edward Nevill edward.nevill@linaro.org
# Date 1399642797 -3600
#      Fri May 09 14:39:57 2014 +0100
# Node ID 1b7ea58b2cf7b5e2dcbdbdecd387abd8bfa30176
# Parent  f67f9b1b52ae8b1778dacb49df641bb5b6e48da1
Optimise C2 entry point verification
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Patch

diff -r f67f9b1b52ae -r 1b7ea58b2cf7 src/cpu/aarch64/vm/aarch64.ad
--- a/src/cpu/aarch64/vm/aarch64.ad	Thu May 01 14:57:36 2014 +0100
+++ b/src/cpu/aarch64/vm/aarch64.ad	Fri May 09 14:39:57 2014 +0100
@@ -1421,9 +1421,8 @@ 
   MacroAssembler _masm(&cbuf);
 
   // no need to worry about 4-byte of br alignment on AArch64
-  __ load_klass(rscratch1, j_rarg0);
+  __ cmp_klass(j_rarg0, rscratch2, rscratch1);
   Label skip;
-  __ cmp(rscratch2, rscratch1);
   // TODO
   // can we avoid this skip and still use a reloc?
   __ br(Assembler::EQ, skip);
diff -r f67f9b1b52ae -r 1b7ea58b2cf7 src/cpu/aarch64/vm/macroAssembler_aarch64.cpp
--- a/src/cpu/aarch64/vm/macroAssembler_aarch64.cpp	Thu May 01 14:57:36 2014 +0100
+++ b/src/cpu/aarch64/vm/macroAssembler_aarch64.cpp	Fri May 09 14:39:57 2014 +0100
@@ -2076,6 +2076,20 @@ 
   }
 }
 
+void MacroAssembler::cmp_klass(Register oop, Register trial_klass, Register tmp) {
+  if (UseCompressedClassPointers) {
+    ldrw(tmp, Address(oop, oopDesc::klass_offset_in_bytes()));
+    if (Universe::narrow_klass_base() == NULL) {
+      cmp(trial_klass, tmp, LSL, Universe::narrow_klass_shift());
+      return;
+    }
+    decode_klass_not_null(tmp);
+  } else {
+    ldr(tmp, Address(oop, oopDesc::klass_offset_in_bytes()));
+  }
+  cmp(trial_klass, tmp);
+}
+
 void MacroAssembler::load_prototype_header(Register dst, Register src) {
   load_klass(dst, src);
   ldr(dst, Address(dst, Klass::prototype_header_offset()));
diff -r f67f9b1b52ae -r 1b7ea58b2cf7 src/cpu/aarch64/vm/macroAssembler_aarch64.hpp
--- a/src/cpu/aarch64/vm/macroAssembler_aarch64.hpp	Thu May 01 14:57:36 2014 +0100
+++ b/src/cpu/aarch64/vm/macroAssembler_aarch64.hpp	Fri May 09 14:39:57 2014 +0100
@@ -703,6 +703,7 @@ 
   // oop manipulations
   void load_klass(Register dst, Register src);
   void store_klass(Register dst, Register src);
+  void cmp_klass(Register oop, Register trial_klass, Register tmp);
 
   void load_heap_oop(Register dst, Address src);
 
--- CUT HERE ---