diff mbox

[v4,3/4] ARM: DRA7: hwmod: Add ocp2scp3 and sata hwmods

Message ID 1398274559-24777-1-git-send-email-rogerq@ti.com
State New
Headers show

Commit Message

Roger Quadros April 23, 2014, 5:35 p.m. UTC
From: Nikhil Devshatwar <nikhil.nd@ti.com>

Add hwmods for ocp2scp3 and sata modules.

[Roger Q] Clean up.

CC: Benoit Cousson <bcousson@baylibre.com>
CC: Paul Walmsley <paul@pwsan.com>
Signed-off-by: Balaji T K <balajitk@ti.com>
Signed-off-by: Nikhil Devshatwar <nikhil.nd@ti.com>
Signed-off-by: Roger Quadros <rogerq@ti.com>
---
 arch/arm/mach-omap2/omap_hwmod_7xx_data.c | 31 ++++++++++++++++++++++++++-----
 1 file changed, 26 insertions(+), 5 deletions(-)

Comments

Roger Quadros June 12, 2014, 12:47 p.m. UTC | #1
Tony,

We need this one as well for 3.16.

cheers,
-roger

On 04/23/2014 08:35 PM, Roger Quadros wrote:
> From: Nikhil Devshatwar <nikhil.nd@ti.com>
> 
> Add hwmods for ocp2scp3 and sata modules.
> 
> [Roger Q] Clean up.
> 
> CC: Benoit Cousson <bcousson@baylibre.com>
> CC: Paul Walmsley <paul@pwsan.com>
> Signed-off-by: Balaji T K <balajitk@ti.com>
> Signed-off-by: Nikhil Devshatwar <nikhil.nd@ti.com>
> Signed-off-by: Roger Quadros <rogerq@ti.com>
> ---
>  arch/arm/mach-omap2/omap_hwmod_7xx_data.c | 31 ++++++++++++++++++++++++++-----
>  1 file changed, 26 insertions(+), 5 deletions(-)
> 
> diff --git a/arch/arm/mach-omap2/omap_hwmod_7xx_data.c b/arch/arm/mach-omap2/omap_hwmod_7xx_data.c
> index 810c205..b02a4ab 100644
> --- a/arch/arm/mach-omap2/omap_hwmod_7xx_data.c
> +++ b/arch/arm/mach-omap2/omap_hwmod_7xx_data.c
> @@ -1215,6 +1215,30 @@ static struct omap_hwmod dra7xx_ocp2scp1_hwmod = {
>  	},
>  };
>  
> +/* ocp2scp3 */
> +static struct omap_hwmod dra7xx_ocp2scp3_hwmod;
> +
> +/* l4_cfg -> ocp2scp3 */
> +static struct omap_hwmod_ocp_if dra7xx_l4_cfg__ocp2scp3 = {
> +	.master		= &dra7xx_l4_cfg_hwmod,
> +	.slave		= &dra7xx_ocp2scp3_hwmod,
> +	.clk		= "l4_root_clk_div",
> +	.user		= OCP_USER_MPU | OCP_USER_SDMA,
> +};
> +
> +static struct omap_hwmod dra7xx_ocp2scp3_hwmod = {
> +	.name		= "ocp2scp3",
> +	.class		= &dra7xx_ocp2scp_hwmod_class,
> +	.clkdm_name	= "l3init_clkdm",
> +	.prcm = {
> +		.omap4 = {
> +			.clkctrl_offs = DRA7XX_CM_L3INIT_OCP2SCP3_CLKCTRL_OFFSET,
> +			.context_offs = DRA7XX_RM_L3INIT_OCP2SCP3_CONTEXT_OFFSET,
> +			.modulemode   = MODULEMODE_HWCTRL,
> +		},
> +	},
> +};
> +
>  /*
>   * 'qspi' class
>   *
> @@ -1268,9 +1292,6 @@ static struct omap_hwmod_class dra7xx_sata_hwmod_class = {
>  };
>  
>  /* sata */
> -static struct omap_hwmod_opt_clk sata_opt_clks[] = {
> -	{ .role = "ref_clk", .clk = "sata_ref_clk" },
> -};
>  
>  static struct omap_hwmod dra7xx_sata_hwmod = {
>  	.name		= "sata",
> @@ -1278,6 +1299,7 @@ static struct omap_hwmod dra7xx_sata_hwmod = {
>  	.clkdm_name	= "l3init_clkdm",
>  	.flags		= HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY,
>  	.main_clk	= "func_48m_fclk",
> +	.mpu_rt_idx	= 1,
>  	.prcm = {
>  		.omap4 = {
>  			.clkctrl_offs = DRA7XX_CM_L3INIT_SATA_CLKCTRL_OFFSET,
> @@ -1285,8 +1307,6 @@ static struct omap_hwmod dra7xx_sata_hwmod = {
>  			.modulemode   = MODULEMODE_SWCTRL,
>  		},
>  	},
> -	.opt_clks	= sata_opt_clks,
> -	.opt_clks_cnt	= ARRAY_SIZE(sata_opt_clks),
>  };
>  
>  /*
> @@ -2682,6 +2702,7 @@ static struct omap_hwmod_ocp_if *dra7xx_hwmod_ocp_ifs[] __initdata = {
>  	&dra7xx_l4_per1__mmc4,
>  	&dra7xx_l4_cfg__mpu,
>  	&dra7xx_l4_cfg__ocp2scp1,
> +	&dra7xx_l4_cfg__ocp2scp3,
>  	&dra7xx_l3_main_1__qspi,
>  	&dra7xx_l4_cfg__sata,
>  	&dra7xx_l4_cfg__smartreflex_core,
> 

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Paul Walmsley June 13, 2014, 7:07 p.m. UTC | #2
Hi Roger,

On Wed, 23 Apr 2014, Roger Quadros wrote:

> From: Nikhil Devshatwar <nikhil.nd@ti.com>
> 
> Add hwmods for ocp2scp3 and sata modules.
> 
> [Roger Q] Clean up.

Sorry for the delay on this.  Have been corresponding with TI to figure 
out what to do about these DRA7xx/AM43xx patches, since I don't have 
boards or public documentation for these devices, so it's impossible for 
me to meaningfully review the patches.  Looks like boards and/or public 
docs won't be coming any time soon.

So for my part, here's what I'll need to merge any hwmod patches that 
involve AM437x or DRA7xx:

1. A Reviewed-by: from one of the following folks (which should come from 
a different person than who is submitting the patches):

Roger Quadros
Nishanth Menon
Rajendra Nayak
Kevin Hilman
Tony Lindgren

2. A Tested-by: from one of the following folks (who can be the same as 
the person who is the same as the person who is submitting the patches):

Nishanth Menon
Rajendra Nayak
Kevin Hilman 
Tony Lindgren

Once these are in place, I'd be happy to queue it for 3.16.


- Paul
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Paul Walmsley June 15, 2014, 3:33 a.m. UTC | #3
On Fri, 13 Jun 2014, Paul Walmsley wrote:

> Hi Roger,
> 
> On Wed, 23 Apr 2014, Roger Quadros wrote:
> 
> > From: Nikhil Devshatwar <nikhil.nd@ti.com>
> > 
> > Add hwmods for ocp2scp3 and sata modules.
> > 
> > [Roger Q] Clean up.
> 
> Sorry for the delay on this.  Have been corresponding with TI to figure 
> out what to do about these DRA7xx/AM43xx patches, since I don't have 
> boards or public documentation for these devices, so it's impossible for 
> me to meaningfully review the patches.  Looks like boards and/or public 
> docs won't be coming any time soon.
> 
> So for my part, here's what I'll need to merge any hwmod patches that 
> involve AM437x or DRA7xx:
> 
> 1. A Reviewed-by: from one of the following folks (which should come from 
> a different person than who is submitting the patches):
> 
> Roger Quadros
> Nishanth Menon
> Rajendra Nayak
> Kevin Hilman
> Tony Lindgren
> 
> 2. A Tested-by: from one of the following folks (who can be the same as 
> the person who is the same as the person who is submitting the patches):
> 
> Nishanth Menon
> Rajendra Nayak
> Kevin Hilman 
> Tony Lindgren
> 
> Once these are in place, I'd be happy to queue it for 3.16.

I've tried to clarify this a bit.  The update is below.


- Paul



For boards that I don't have access to, that I don't have 
documentation for, such as the AM43xx and DRA7xx), for me to merge or ack 
SoC infrastructure or PM-related patches, I want to have:

1. a Reviewed-by: from people who:

a. I think know something about SoC integration or PM in general, and 
about OMAP-style integration specifically; and

b. who have a track record of doing strong and detailed reviews of that 
code, or who have contributed significantly to that code in the past.

My initial list of those reviewers is listed above, and I am happy to 
consider extending it or modifying that list.


2. confidence that the patch or series has been tested against a mainline 
commit and isn't obviously breaking other things, like PM, and confidence 
that it's not adding new runtime warnings.

I've listed an initial set of people above who I feel have proven track 
records in testing who I'm happy to accept Tested-by:s without further 
explanation.  I'm sure I've missed some folks and if anyone who should be 
on that list is offended that I didn't mention them, please accept my 
apologies.  For other folks, like yourself, who aren't on that list (yet), 
please just specifically state:

a. what mainline commit they've tested the patch against,

b. what other prerequisite patches were needed for the patch to apply,

c. and a cut-and-paste of the serial console boot log from the boot 
portion of the test.

in such a way that myself or someone else can easily doublecheck it. 

And frankly, I'll probably be happy to merge it.

After someone has done these three things a few times, and I gain 
confidence that they're doing the right thing, I'm happy to add them to 
my list.

The testing doesn't have to be expressed via a Tested-by: tag in cases 
where you're testing as part of a Signed-off-by:.  Just be sure to state 
those three things above as part of the patch or series message.  The boot 
log can either be placed on a different page and linked to, or sent in 
another public E-mail.

If you can get two or three people to do the above, that's great - the 
more, the better.

...

These two steps do not apply to boards that I have in my testbed or which 
I have documentation for (although they would definitely be very welcome 
in those cases too).

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Roger Quadros June 18, 2014, 7:56 a.m. UTC | #4
+ Rajendra, Nishant and Kevin.
as you were mentioned in the discussion.

cheers,
-roger

On 06/15/2014 06:33 AM, Paul Walmsley wrote:
> On Fri, 13 Jun 2014, Paul Walmsley wrote:
> 
>> Hi Roger,
>>
>> On Wed, 23 Apr 2014, Roger Quadros wrote:
>>
>>> From: Nikhil Devshatwar <nikhil.nd@ti.com>
>>>
>>> Add hwmods for ocp2scp3 and sata modules.
>>>
>>> [Roger Q] Clean up.
>>
>> Sorry for the delay on this.  Have been corresponding with TI to figure 
>> out what to do about these DRA7xx/AM43xx patches, since I don't have 
>> boards or public documentation for these devices, so it's impossible for 
>> me to meaningfully review the patches.  Looks like boards and/or public 
>> docs won't be coming any time soon.
>>
>> So for my part, here's what I'll need to merge any hwmod patches that 
>> involve AM437x or DRA7xx:
>>
>> 1. A Reviewed-by: from one of the following folks (which should come from 
>> a different person than who is submitting the patches):
>>
>> Roger Quadros
>> Nishanth Menon
>> Rajendra Nayak
>> Kevin Hilman
>> Tony Lindgren
>>
>> 2. A Tested-by: from one of the following folks (who can be the same as 
>> the person who is the same as the person who is submitting the patches):
>>
>> Nishanth Menon
>> Rajendra Nayak
>> Kevin Hilman 
>> Tony Lindgren
>>
>> Once these are in place, I'd be happy to queue it for 3.16.
> 
> I've tried to clarify this a bit.  The update is below.
> 
> 
> - Paul
> 
> 
> 
> For boards that I don't have access to, that I don't have 
> documentation for, such as the AM43xx and DRA7xx), for me to merge or ack 
> SoC infrastructure or PM-related patches, I want to have:
> 
> 1. a Reviewed-by: from people who:
> 
> a. I think know something about SoC integration or PM in general, and 
> about OMAP-style integration specifically; and
> 
> b. who have a track record of doing strong and detailed reviews of that 
> code, or who have contributed significantly to that code in the past.
> 
> My initial list of those reviewers is listed above, and I am happy to 
> consider extending it or modifying that list.
> 
> 
> 2. confidence that the patch or series has been tested against a mainline 
> commit and isn't obviously breaking other things, like PM, and confidence 
> that it's not adding new runtime warnings.
> 
> I've listed an initial set of people above who I feel have proven track 
> records in testing who I'm happy to accept Tested-by:s without further 
> explanation.  I'm sure I've missed some folks and if anyone who should be 
> on that list is offended that I didn't mention them, please accept my 
> apologies.  For other folks, like yourself, who aren't on that list (yet), 
> please just specifically state:
> 
> a. what mainline commit they've tested the patch against,
> 
> b. what other prerequisite patches were needed for the patch to apply,
> 
> c. and a cut-and-paste of the serial console boot log from the boot 
> portion of the test.
> 
> in such a way that myself or someone else can easily doublecheck it. 
> 
> And frankly, I'll probably be happy to merge it.
> 
> After someone has done these three things a few times, and I gain 
> confidence that they're doing the right thing, I'm happy to add them to 
> my list.
> 
> The testing doesn't have to be expressed via a Tested-by: tag in cases 
> where you're testing as part of a Signed-off-by:.  Just be sure to state 
> those three things above as part of the patch or series message.  The boot 
> log can either be placed on a different page and linked to, or sent in 
> another public E-mail.
> 
> If you can get two or three people to do the above, that's great - the 
> more, the better.
> 
> ...
> 
> These two steps do not apply to boards that I have in my testbed or which 
> I have documentation for (although they would definitely be very welcome 
> in those cases too).
> 

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Roger Quadros June 18, 2014, 8:02 a.m. UTC | #5
On 04/23/2014 08:35 PM, Roger Quadros wrote:
> From: Nikhil Devshatwar <nikhil.nd@ti.com>
> 
> Add hwmods for ocp2scp3 and sata modules.
> 
> [Roger Q] Clean up.
> 
> CC: Benoit Cousson <bcousson@baylibre.com>
> CC: Paul Walmsley <paul@pwsan.com>
> Signed-off-by: Balaji T K <balajitk@ti.com>
> Signed-off-by: Nikhil Devshatwar <nikhil.nd@ti.com>
> Signed-off-by: Roger Quadros <rogerq@ti.com>

Tested-by: Roger Quadros <rogerq@ti.com>
against 3.16-rc1, no dependency patches needed.

Nishant/Rajendra,

Could you please review this? We need this for 3.16 SATA support and
Paul won't take this in without your reviewed-by tag. Thanks.

cheers,
-roger

> ---
>  arch/arm/mach-omap2/omap_hwmod_7xx_data.c | 31 ++++++++++++++++++++++++++-----
>  1 file changed, 26 insertions(+), 5 deletions(-)
> 
> diff --git a/arch/arm/mach-omap2/omap_hwmod_7xx_data.c b/arch/arm/mach-omap2/omap_hwmod_7xx_data.c
> index 810c205..b02a4ab 100644
> --- a/arch/arm/mach-omap2/omap_hwmod_7xx_data.c
> +++ b/arch/arm/mach-omap2/omap_hwmod_7xx_data.c
> @@ -1215,6 +1215,30 @@ static struct omap_hwmod dra7xx_ocp2scp1_hwmod = {
>  	},
>  };
>  
> +/* ocp2scp3 */
> +static struct omap_hwmod dra7xx_ocp2scp3_hwmod;
> +
> +/* l4_cfg -> ocp2scp3 */
> +static struct omap_hwmod_ocp_if dra7xx_l4_cfg__ocp2scp3 = {
> +	.master		= &dra7xx_l4_cfg_hwmod,
> +	.slave		= &dra7xx_ocp2scp3_hwmod,
> +	.clk		= "l4_root_clk_div",
> +	.user		= OCP_USER_MPU | OCP_USER_SDMA,
> +};
> +
> +static struct omap_hwmod dra7xx_ocp2scp3_hwmod = {
> +	.name		= "ocp2scp3",
> +	.class		= &dra7xx_ocp2scp_hwmod_class,
> +	.clkdm_name	= "l3init_clkdm",
> +	.prcm = {
> +		.omap4 = {
> +			.clkctrl_offs = DRA7XX_CM_L3INIT_OCP2SCP3_CLKCTRL_OFFSET,
> +			.context_offs = DRA7XX_RM_L3INIT_OCP2SCP3_CONTEXT_OFFSET,
> +			.modulemode   = MODULEMODE_HWCTRL,
> +		},
> +	},
> +};
> +
>  /*
>   * 'qspi' class
>   *
> @@ -1268,9 +1292,6 @@ static struct omap_hwmod_class dra7xx_sata_hwmod_class = {
>  };
>  
>  /* sata */
> -static struct omap_hwmod_opt_clk sata_opt_clks[] = {
> -	{ .role = "ref_clk", .clk = "sata_ref_clk" },
> -};
>  
>  static struct omap_hwmod dra7xx_sata_hwmod = {
>  	.name		= "sata",
> @@ -1278,6 +1299,7 @@ static struct omap_hwmod dra7xx_sata_hwmod = {
>  	.clkdm_name	= "l3init_clkdm",
>  	.flags		= HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY,
>  	.main_clk	= "func_48m_fclk",
> +	.mpu_rt_idx	= 1,
>  	.prcm = {
>  		.omap4 = {
>  			.clkctrl_offs = DRA7XX_CM_L3INIT_SATA_CLKCTRL_OFFSET,
> @@ -1285,8 +1307,6 @@ static struct omap_hwmod dra7xx_sata_hwmod = {
>  			.modulemode   = MODULEMODE_SWCTRL,
>  		},
>  	},
> -	.opt_clks	= sata_opt_clks,
> -	.opt_clks_cnt	= ARRAY_SIZE(sata_opt_clks),
>  };
>  
>  /*
> @@ -2682,6 +2702,7 @@ static struct omap_hwmod_ocp_if *dra7xx_hwmod_ocp_ifs[] __initdata = {
>  	&dra7xx_l4_per1__mmc4,
>  	&dra7xx_l4_cfg__mpu,
>  	&dra7xx_l4_cfg__ocp2scp1,
> +	&dra7xx_l4_cfg__ocp2scp3,
>  	&dra7xx_l3_main_1__qspi,
>  	&dra7xx_l4_cfg__sata,
>  	&dra7xx_l4_cfg__smartreflex_core,
> 

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Rajendra Nayak June 18, 2014, 10:29 a.m. UTC | #6
On Wednesday 18 June 2014 01:32 PM, Roger Quadros wrote:
> On 04/23/2014 08:35 PM, Roger Quadros wrote:
>> From: Nikhil Devshatwar <nikhil.nd@ti.com>
>>
>> Add hwmods for ocp2scp3 and sata modules.

From what I see this is actually adding the ocp2scp3 data and fixing up some
of the sata data which is already added and erroneous.

It would help if this is split up and the changelog explains whats fixed up for
sata and why. Like for instance I see the opt clock data being removed but no
mention of why.
 
>>
>> [Roger Q] Clean up.
>>
>> CC: Benoit Cousson <bcousson@baylibre.com>
>> CC: Paul Walmsley <paul@pwsan.com>
>> Signed-off-by: Balaji T K <balajitk@ti.com>
>> Signed-off-by: Nikhil Devshatwar <nikhil.nd@ti.com>
>> Signed-off-by: Roger Quadros <rogerq@ti.com>
> 
> Tested-by: Roger Quadros <rogerq@ti.com>
> against 3.16-rc1, no dependency patches needed.
> 
> Nishant/Rajendra,
> 
> Could you please review this? We need this for 3.16 SATA support and
> Paul won't take this in without your reviewed-by tag. Thanks.
> 
> cheers,
> -roger
> 
>> ---
>>  arch/arm/mach-omap2/omap_hwmod_7xx_data.c | 31 ++++++++++++++++++++++++++-----
>>  1 file changed, 26 insertions(+), 5 deletions(-)
>>
>> diff --git a/arch/arm/mach-omap2/omap_hwmod_7xx_data.c b/arch/arm/mach-omap2/omap_hwmod_7xx_data.c
>> index 810c205..b02a4ab 100644
>> --- a/arch/arm/mach-omap2/omap_hwmod_7xx_data.c
>> +++ b/arch/arm/mach-omap2/omap_hwmod_7xx_data.c
>> @@ -1215,6 +1215,30 @@ static struct omap_hwmod dra7xx_ocp2scp1_hwmod = {
>>  	},
>>  };
>>  
>> +/* ocp2scp3 */
>> +static struct omap_hwmod dra7xx_ocp2scp3_hwmod;
>> +
>> +/* l4_cfg -> ocp2scp3 */
>> +static struct omap_hwmod_ocp_if dra7xx_l4_cfg__ocp2scp3 = {
>> +	.master		= &dra7xx_l4_cfg_hwmod,
>> +	.slave		= &dra7xx_ocp2scp3_hwmod,
>> +	.clk		= "l4_root_clk_div",
>> +	.user		= OCP_USER_MPU | OCP_USER_SDMA,
>> +};

All hwmod data files are organized in a certain way with all the hwmod/IP block info on top
and Interface structs at the bottom. Can we follow the same for ocp2scp3? It helps with better
readability.
 
>> +
>> +static struct omap_hwmod dra7xx_ocp2scp3_hwmod = {
>> +	.name		= "ocp2scp3",
>> +	.class		= &dra7xx_ocp2scp_hwmod_class,
>> +	.clkdm_name	= "l3init_clkdm",

No main_clk?

regards,
Rajendra

>> +	.prcm = {
>> +		.omap4 = {
>> +			.clkctrl_offs = DRA7XX_CM_L3INIT_OCP2SCP3_CLKCTRL_OFFSET,
>> +			.context_offs = DRA7XX_RM_L3INIT_OCP2SCP3_CONTEXT_OFFSET,
>> +			.modulemode   = MODULEMODE_HWCTRL,
>> +		},
>> +	},
>> +};
>> +
>>  /*
>>   * 'qspi' class
>>   *
>> @@ -1268,9 +1292,6 @@ static struct omap_hwmod_class dra7xx_sata_hwmod_class = {
>>  };
>>  
>>  /* sata */
>> -static struct omap_hwmod_opt_clk sata_opt_clks[] = {
>> -	{ .role = "ref_clk", .clk = "sata_ref_clk" },
>> -};
>>  
>>  static struct omap_hwmod dra7xx_sata_hwmod = {
>>  	.name		= "sata",
>> @@ -1278,6 +1299,7 @@ static struct omap_hwmod dra7xx_sata_hwmod = {
>>  	.clkdm_name	= "l3init_clkdm",
>>  	.flags		= HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY,
>>  	.main_clk	= "func_48m_fclk",
>> +	.mpu_rt_idx	= 1,
>>  	.prcm = {
>>  		.omap4 = {
>>  			.clkctrl_offs = DRA7XX_CM_L3INIT_SATA_CLKCTRL_OFFSET,
>> @@ -1285,8 +1307,6 @@ static struct omap_hwmod dra7xx_sata_hwmod = {
>>  			.modulemode   = MODULEMODE_SWCTRL,
>>  		},
>>  	},
>> -	.opt_clks	= sata_opt_clks,
>> -	.opt_clks_cnt	= ARRAY_SIZE(sata_opt_clks),
>>  };
>>  
>>  /*
>> @@ -2682,6 +2702,7 @@ static struct omap_hwmod_ocp_if *dra7xx_hwmod_ocp_ifs[] __initdata = {
>>  	&dra7xx_l4_per1__mmc4,
>>  	&dra7xx_l4_cfg__mpu,
>>  	&dra7xx_l4_cfg__ocp2scp1,
>> +	&dra7xx_l4_cfg__ocp2scp3,
>>  	&dra7xx_l3_main_1__qspi,
>>  	&dra7xx_l4_cfg__sata,
>>  	&dra7xx_l4_cfg__smartreflex_core,
>>
> 

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Roger Quadros June 18, 2014, 11:22 a.m. UTC | #7
On 06/18/2014 01:29 PM, Rajendra Nayak wrote:
> On Wednesday 18 June 2014 01:32 PM, Roger Quadros wrote:
>> On 04/23/2014 08:35 PM, Roger Quadros wrote:
>>> From: Nikhil Devshatwar <nikhil.nd@ti.com>
>>>
>>> Add hwmods for ocp2scp3 and sata modules.
> 
> From what I see this is actually adding the ocp2scp3 data and fixing up some
> of the sata data which is already added and erroneous.
> 
> It would help if this is split up and the changelog explains whats fixed up for
> sata and why. Like for instance I see the opt clock data being removed but no
> mention of why.

OK. I will split this up into 2 patches, one to add ocp2scp3 data and the other to fix sata hwmod.

cheers,
-roger

>  
>>>
>>> [Roger Q] Clean up.
>>>
>>> CC: Benoit Cousson <bcousson@baylibre.com>
>>> CC: Paul Walmsley <paul@pwsan.com>
>>> Signed-off-by: Balaji T K <balajitk@ti.com>
>>> Signed-off-by: Nikhil Devshatwar <nikhil.nd@ti.com>
>>> Signed-off-by: Roger Quadros <rogerq@ti.com>
>>
>> Tested-by: Roger Quadros <rogerq@ti.com>
>> against 3.16-rc1, no dependency patches needed.
>>
>> Nishant/Rajendra,
>>
>> Could you please review this? We need this for 3.16 SATA support and
>> Paul won't take this in without your reviewed-by tag. Thanks.
>>
>> cheers,
>> -roger
>>
>>> ---
>>>  arch/arm/mach-omap2/omap_hwmod_7xx_data.c | 31 ++++++++++++++++++++++++++-----
>>>  1 file changed, 26 insertions(+), 5 deletions(-)
>>>
>>> diff --git a/arch/arm/mach-omap2/omap_hwmod_7xx_data.c b/arch/arm/mach-omap2/omap_hwmod_7xx_data.c
>>> index 810c205..b02a4ab 100644
>>> --- a/arch/arm/mach-omap2/omap_hwmod_7xx_data.c
>>> +++ b/arch/arm/mach-omap2/omap_hwmod_7xx_data.c
>>> @@ -1215,6 +1215,30 @@ static struct omap_hwmod dra7xx_ocp2scp1_hwmod = {
>>>  	},
>>>  };
>>>  
>>> +/* ocp2scp3 */
>>> +static struct omap_hwmod dra7xx_ocp2scp3_hwmod;
>>> +
>>> +/* l4_cfg -> ocp2scp3 */
>>> +static struct omap_hwmod_ocp_if dra7xx_l4_cfg__ocp2scp3 = {
>>> +	.master		= &dra7xx_l4_cfg_hwmod,
>>> +	.slave		= &dra7xx_ocp2scp3_hwmod,
>>> +	.clk		= "l4_root_clk_div",
>>> +	.user		= OCP_USER_MPU | OCP_USER_SDMA,
>>> +};
> 
> All hwmod data files are organized in a certain way with all the hwmod/IP block info on top
> and Interface structs at the bottom. Can we follow the same for ocp2scp3? It helps with better
> readability.
>  
>>> +
>>> +static struct omap_hwmod dra7xx_ocp2scp3_hwmod = {
>>> +	.name		= "ocp2scp3",
>>> +	.class		= &dra7xx_ocp2scp_hwmod_class,
>>> +	.clkdm_name	= "l3init_clkdm",
> 
> No main_clk?
> 
> regards,
> Rajendra
> 
>>> +	.prcm = {
>>> +		.omap4 = {
>>> +			.clkctrl_offs = DRA7XX_CM_L3INIT_OCP2SCP3_CLKCTRL_OFFSET,
>>> +			.context_offs = DRA7XX_RM_L3INIT_OCP2SCP3_CONTEXT_OFFSET,
>>> +			.modulemode   = MODULEMODE_HWCTRL,
>>> +		},
>>> +	},
>>> +};
>>> +
>>>  /*
>>>   * 'qspi' class
>>>   *
>>> @@ -1268,9 +1292,6 @@ static struct omap_hwmod_class dra7xx_sata_hwmod_class = {
>>>  };
>>>  
>>>  /* sata */
>>> -static struct omap_hwmod_opt_clk sata_opt_clks[] = {
>>> -	{ .role = "ref_clk", .clk = "sata_ref_clk" },
>>> -};
>>>  
>>>  static struct omap_hwmod dra7xx_sata_hwmod = {
>>>  	.name		= "sata",
>>> @@ -1278,6 +1299,7 @@ static struct omap_hwmod dra7xx_sata_hwmod = {
>>>  	.clkdm_name	= "l3init_clkdm",
>>>  	.flags		= HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY,
>>>  	.main_clk	= "func_48m_fclk",
>>> +	.mpu_rt_idx	= 1,
>>>  	.prcm = {
>>>  		.omap4 = {
>>>  			.clkctrl_offs = DRA7XX_CM_L3INIT_SATA_CLKCTRL_OFFSET,
>>> @@ -1285,8 +1307,6 @@ static struct omap_hwmod dra7xx_sata_hwmod = {
>>>  			.modulemode   = MODULEMODE_SWCTRL,
>>>  		},
>>>  	},
>>> -	.opt_clks	= sata_opt_clks,
>>> -	.opt_clks_cnt	= ARRAY_SIZE(sata_opt_clks),
>>>  };
>>>  
>>>  /*
>>> @@ -2682,6 +2702,7 @@ static struct omap_hwmod_ocp_if *dra7xx_hwmod_ocp_ifs[] __initdata = {
>>>  	&dra7xx_l4_per1__mmc4,
>>>  	&dra7xx_l4_cfg__mpu,
>>>  	&dra7xx_l4_cfg__ocp2scp1,
>>> +	&dra7xx_l4_cfg__ocp2scp3,
>>>  	&dra7xx_l3_main_1__qspi,
>>>  	&dra7xx_l4_cfg__sata,
>>>  	&dra7xx_l4_cfg__smartreflex_core,
>>>
>>
> 

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diff mbox

Patch

diff --git a/arch/arm/mach-omap2/omap_hwmod_7xx_data.c b/arch/arm/mach-omap2/omap_hwmod_7xx_data.c
index 810c205..b02a4ab 100644
--- a/arch/arm/mach-omap2/omap_hwmod_7xx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_7xx_data.c
@@ -1215,6 +1215,30 @@  static struct omap_hwmod dra7xx_ocp2scp1_hwmod = {
 	},
 };
 
+/* ocp2scp3 */
+static struct omap_hwmod dra7xx_ocp2scp3_hwmod;
+
+/* l4_cfg -> ocp2scp3 */
+static struct omap_hwmod_ocp_if dra7xx_l4_cfg__ocp2scp3 = {
+	.master		= &dra7xx_l4_cfg_hwmod,
+	.slave		= &dra7xx_ocp2scp3_hwmod,
+	.clk		= "l4_root_clk_div",
+	.user		= OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+static struct omap_hwmod dra7xx_ocp2scp3_hwmod = {
+	.name		= "ocp2scp3",
+	.class		= &dra7xx_ocp2scp_hwmod_class,
+	.clkdm_name	= "l3init_clkdm",
+	.prcm = {
+		.omap4 = {
+			.clkctrl_offs = DRA7XX_CM_L3INIT_OCP2SCP3_CLKCTRL_OFFSET,
+			.context_offs = DRA7XX_RM_L3INIT_OCP2SCP3_CONTEXT_OFFSET,
+			.modulemode   = MODULEMODE_HWCTRL,
+		},
+	},
+};
+
 /*
  * 'qspi' class
  *
@@ -1268,9 +1292,6 @@  static struct omap_hwmod_class dra7xx_sata_hwmod_class = {
 };
 
 /* sata */
-static struct omap_hwmod_opt_clk sata_opt_clks[] = {
-	{ .role = "ref_clk", .clk = "sata_ref_clk" },
-};
 
 static struct omap_hwmod dra7xx_sata_hwmod = {
 	.name		= "sata",
@@ -1278,6 +1299,7 @@  static struct omap_hwmod dra7xx_sata_hwmod = {
 	.clkdm_name	= "l3init_clkdm",
 	.flags		= HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY,
 	.main_clk	= "func_48m_fclk",
+	.mpu_rt_idx	= 1,
 	.prcm = {
 		.omap4 = {
 			.clkctrl_offs = DRA7XX_CM_L3INIT_SATA_CLKCTRL_OFFSET,
@@ -1285,8 +1307,6 @@  static struct omap_hwmod dra7xx_sata_hwmod = {
 			.modulemode   = MODULEMODE_SWCTRL,
 		},
 	},
-	.opt_clks	= sata_opt_clks,
-	.opt_clks_cnt	= ARRAY_SIZE(sata_opt_clks),
 };
 
 /*
@@ -2682,6 +2702,7 @@  static struct omap_hwmod_ocp_if *dra7xx_hwmod_ocp_ifs[] __initdata = {
 	&dra7xx_l4_per1__mmc4,
 	&dra7xx_l4_cfg__mpu,
 	&dra7xx_l4_cfg__ocp2scp1,
+	&dra7xx_l4_cfg__ocp2scp3,
 	&dra7xx_l3_main_1__qspi,
 	&dra7xx_l4_cfg__sata,
 	&dra7xx_l4_cfg__smartreflex_core,