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[v2,14/17] target/riscv: Only support little endian guests

Message ID 7faee43fc9a209a9c801e0a543a51b09a479331a.1591319882.git.alistair@alistair23.me
State Superseded
Headers show
Series RISC-V: Update the Hypervisor spec to v0.6.1 | expand

Commit Message

Alistair Francis June 5, 2020, 1:21 a.m. UTC 
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/csr.c | 5 +++++
 1 file changed, 5 insertions(+)
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Patch

diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index 973404d0aa..5b64539efb 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -772,6 +772,8 @@  static int read_hstatus(CPURISCVState *env, int csrno, target_ulong *val)
     /* We only support 64-bit VSXL */
     *val = set_field(*val, HSTATUS_VSXL, 2);
 #endif
+    /* We only support little endian */
+    *val = set_field(*val, HSTATUS_VSBE, 0);
     return 0;
 }
 
@@ -783,6 +785,9 @@  static int write_hstatus(CPURISCVState *env, int csrno, target_ulong val)
         qemu_log_mask(LOG_UNIMP, "QEMU does not support mixed HSXLEN options.");
     }
 #endif
+    if (get_field(val, HSTATUS_VSBE) != 0) {
+        qemu_log_mask(LOG_UNIMP, "QEMU does not support big endian guests.");
+    }
     return 0;
 }