[RFC,12/14] arm/: fix some comment spelling errors

I found that there are many spelling errors in the comments of qemu/target/arm.
I used spellcheck to check the spelling errors and found some errors in the folder.

Signed-off-by: zhaolichang <zhaolichang@huawei.com>
---
 target/arm/cpu.h           | 2 +-
 target/arm/helper.c        | 4 ++--
 target/arm/m_helper.c      | 2 +-
 target/arm/translate-a64.c | 4 ++--
 target/arm/translate-sve.c | 2 +-
 5 files changed, 7 insertions(+), 7 deletions(-)

On Wednesday, 2020-09-30 at 17:53:19 +08, zhaolichang wrote:

> I found that there are many spelling errors in the comments of qemu/target/arm.
> I used spellcheck to check the spelling errors and found some errors in the folder.
>
> Signed-off-by: zhaolichang <zhaolichang@huawei.com>

Reviewed-by: David Edmondson <david.edmondson@oracle.com>

> ---
>  target/arm/cpu.h           | 2 +-
>  target/arm/helper.c        | 4 ++--
>  target/arm/m_helper.c      | 2 +-
>  target/arm/translate-a64.c | 4 ++--
>  target/arm/translate-sve.c | 2 +-
>  5 files changed, 7 insertions(+), 7 deletions(-)
>
> diff --git a/target/arm/cpu.h b/target/arm/cpu.h
> index 6036f61..996308b 100644
> --- a/target/arm/cpu.h
> +++ b/target/arm/cpu.h
> @@ -2067,7 +2067,7 @@ static inline bool arm_el_is_aa64(CPUARMState *env, int el)
>      return aa64;
>  }
>  
> -/* Function for determing whether guest cp register reads and writes should
> +/* Function for determining whether guest cp register reads and writes should
>   * access the secure or non-secure bank of a cp register.  When EL3 is
>   * operating in AArch32 state, the NS-bit determines whether the secure
>   * instance of a cp register should be used. When EL3 is AArch64 (or if
> diff --git a/target/arm/helper.c b/target/arm/helper.c
> index 88bd9dd..9292e16 100644
> --- a/target/arm/helper.c
> +++ b/target/arm/helper.c
> @@ -1867,7 +1867,7 @@ static void pmevtyper_rawwrite(CPUARMState *env, const ARMCPRegInfo *ri,
>       * pmevtyper_rawwrite is called between a pair of pmu_op_start and
>       * pmu_op_finish calls when loading saved state for a migration. Because
>       * we're potentially updating the type of event here, the value written to
> -     * c14_pmevcntr_delta by the preceeding pmu_op_start call may be for a
> +     * c14_pmevcntr_delta by the preceding pmu_op_start call may be for a
>       * different counter type. Therefore, we need to set this value to the
>       * current count for the counter type we're writing so that pmu_op_finish
>       * has the correct count for its calculation.
> @@ -12214,7 +12214,7 @@ bool get_phys_addr(CPUARMState *env, target_ulong address,
>              } else {
>                  memattr = 0x44;  /* Normal, NC, No */
>              }
> -            cacheattrs->shareability = 2; /* outer sharable */
> +            cacheattrs->shareability = 2; /* outer shareable */
>          } else {
>              memattr = 0x00;      /* Device, nGnRnE */
>          }
> diff --git a/target/arm/m_helper.c b/target/arm/m_helper.c
> index 0364542..1e8080d 100644
> --- a/target/arm/m_helper.c
> +++ b/target/arm/m_helper.c
> @@ -158,7 +158,7 @@ uint32_t HELPER(v7m_tt)(CPUARMState *env, uint32_t addr, uint32_t op)
>       *  R: 0 because unpriv and A flag not set
>       *  SRVALID: 0 because NS
>       *  MRVALID: 0 because unpriv and A flag not set
> -     *  SREGION: 0 becaus SRVALID is 0
> +     *  SREGION: 0 because SRVALID is 0
>       *  MREGION: 0 because MRVALID is 0
>       */
>      return 0;
> diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
> index 7188808..5451f02 100644
> --- a/target/arm/translate-a64.c
> +++ b/target/arm/translate-a64.c
> @@ -160,7 +160,7 @@ void gen_a64_set_pc_im(uint64_t val)
>   *  + for EL2 and EL3 there is only one TBI bit, and if it is set
>   *    then the address is zero-extended, clearing bits [63:56]
>   *  + for EL0 and EL1, TBI0 controls addresses with bit 55 == 0
> - *    and TBI1 controls addressses with bit 55 == 1.
> + *    and TBI1 controls addresses with bit 55 == 1.
>   *    If the appropriate TBI bit is set for the address then
>   *    the address is sign-extended from bit 55 into bits [63:56]
>   *
> @@ -1964,7 +1964,7 @@ static void handle_sys(DisasContext *s, uint32_t insn, bool isread,
>      }
>      if (!isread && !(ri->type & ARM_CP_SUPPRESS_TB_END)) {
>          /*
> -         * A write to any coprocessor regiser that ends a TB
> +         * A write to any coprocessor register that ends a TB
>           * must rebuild the hflags for the next TB.
>           */
>          TCGv_i32 tcg_el = tcg_const_i32(s->current_el);
> diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
> index e4cd6b6..4e8a1c7 100644
> --- a/target/arm/translate-sve.c
> +++ b/target/arm/translate-sve.c
> @@ -1528,7 +1528,7 @@ static bool trans_PNEXT(DisasContext *s, arg_rr_esz *a)
>  
>  /* Perform an inline saturating addition of a 32-bit value within
>   * a 64-bit register.  The second operand is known to be positive,
> - * which halves the comparisions we must perform to bound the result.
> + * which halves the comparisons we must perform to bound the result.
>   */
>  static void do_sat_addsub_32(TCGv_i64 reg, TCGv_i64 val, bool u, bool d)
>  {
> -- 
> 2.26.2.windows.1

dme.

On 9/30/20 11:53 AM, zhaolichang wrote:
> I found that there are many spelling errors in the comments of qemu/target/arm.

> I used spellcheck to check the spelling errors and found some errors in the folder.

> 

> Signed-off-by: zhaolichang <zhaolichang@huawei.com>

> ---

>  target/arm/cpu.h           | 2 +-

>  target/arm/helper.c        | 4 ++--

>  target/arm/m_helper.c      | 2 +-

>  target/arm/translate-a64.c | 4 ++--

>  target/arm/translate-sve.c | 2 +-

>  5 files changed, 7 insertions(+), 7 deletions(-)


Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>