| Message ID | 20201013085207.17749-4-chunfeng.yun@mediatek.com |
|---|---|
| State | New |
| Headers | show |
| Series | [v2,1/8] dt-bindings: phy: convert phy-mtk-xsphy.txt to YAML schema | expand |
Hi, Chunfeng: On Tue, 2020-10-13 at 16:52 +0800, Chunfeng Yun wrote: > Convert HDMI PHY binding to YAML schema mediatek,ufs-phy.yaml > > Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> > --- > v2: fix binding check warning of reg in example > --- > .../display/mediatek/mediatek,hdmi.txt | 17 +--- > .../bindings/phy/mediatek,hdmi-phy.yaml | 90 +++++++++++++++++++ > 2 files changed, 91 insertions(+), 16 deletions(-) > create mode 100644 Documentation/devicetree/bindings/phy/mediatek,hdmi-phy.yaml > > diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,hdmi.txt b/Documentation/devicetree/bindings/display/mediatek/mediatek,hdmi.txt > index 7b124242b0c5..edac18951a75 100644 > --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,hdmi.txt > +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,hdmi.txt > @@ -50,22 +50,7 @@ Required properties: > > HDMI PHY > ======== > - > -The HDMI PHY serializes the HDMI encoder's three channel 10-bit parallel > -output and drives the HDMI pads. > - > -Required properties: > -- compatible: "mediatek,<chip>-hdmi-phy" > -- reg: Physical base address and length of the module's registers > -- clocks: PLL reference clock > -- clock-names: must contain "pll_ref" > -- clock-output-names: must be "hdmitx_dig_cts" on mt8173 > -- #phy-cells: must be <0> > -- #clock-cells: must be <0> > - > -Optional properties: > -- mediatek,ibias: TX DRV bias current for <1.65Gbps, defaults to 0xa > -- mediatek,ibias_up: TX DRV bias current for >1.65Gbps, defaults to 0x1c > +See phy/mediatek,hdmi-phy.yaml > > Example: > > diff --git a/Documentation/devicetree/bindings/phy/mediatek,hdmi-phy.yaml b/Documentation/devicetree/bindings/phy/mediatek,hdmi-phy.yaml > new file mode 100644 > index 000000000000..77df50204606 > --- /dev/null > +++ b/Documentation/devicetree/bindings/phy/mediatek,hdmi-phy.yaml > @@ -0,0 +1,90 @@ > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > +# Copyright (c) 2020 MediaTek > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/phy/mediatek,hdmi-phy.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: MediaTek High Definition Multimedia Interface (HDMI) PHY binding > + > +maintainers: > + - CK Hu <ck.hu@mediatek.com> I think you should remove "CK Hu <ck.hu@mediatek.com>" and add latest mediatek drm maintainer: DRM DRIVERS FOR MEDIATEK M: Chun-Kuang Hu <chunkuang.hu@kernel.org> M: Philipp Zabel <p.zabel@pengutronix.de> L: dri-devel@lists.freedesktop.org S: Supported F: Documentation/devicetree/bindings/display/mediatek/ F: drivers/gpu/drm/mediatek/ Regards, CK > + - Chunfeng Yun <chunfeng.yun@mediatek.com> > + > +description: | > + The HDMI PHY serializes the HDMI encoder's three channel 10-bit parallel > + output and drives the HDMI pads. > + > +properties: > + $nodename: > + pattern: "^hdmi-phy@[0-9a-f]+$" > + > + compatible: > + enum: > + - mediatek,mt2701-hdmi-phy > + - mediatek,mt8173-hdmi-phy > + > + reg: > + maxItems: 1 > + > + clocks: > + items: > + - description: PLL reference clock > + > + clock-names: > + items: > + - const: pll_ref > + > + clock-output-names: > + items: > + - const: hdmitx_dig_cts > + > + "#phy-cells": > + const: 0 > + > + "#clock-cells": > + const: 0 > + > + mediatek,ibias: > + description: > + TX DRV bias current for < 1.65Gbps > + $ref: /schemas/types.yaml#/definitions/uint32 > + minimum: 0 > + maximum: 63 > + default: 0xa > + > + mediatek,ibias_up: > + description: > + TX DRV bias current for >= 1.65Gbps > + $ref: /schemas/types.yaml#/definitions/uint32 > + minimum: 0 > + maximum: 63 > + default: 0x1c > + > +required: > + - compatible > + - reg > + - clocks > + - clock-names > + - clock-output-names > + - "#phy-cells" > + - "#clock-cells" > + > +additionalProperties: false > + > +examples: > + - | > + #include <dt-bindings/clock/mt8173-clk.h> > + hdmi_phy: hdmi-phy@10209100 { > + compatible = "mediatek,mt8173-hdmi-phy"; > + reg = <0x10209100 0x24>; > + clocks = <&apmixedsys CLK_APMIXED_HDMI_REF>; > + clock-names = "pll_ref"; > + clock-output-names = "hdmitx_dig_cts"; > + mediatek,ibias = <0xa>; > + mediatek,ibias_up = <0x1c>; > + #clock-cells = <0>; > + #phy-cells = <0>; > + }; > + > +...
On Wed, 2020-10-14 at 12:44 +0800, CK Hu wrote: > Hi, Chunfeng: > > On Tue, 2020-10-13 at 16:52 +0800, Chunfeng Yun wrote: > > Convert HDMI PHY binding to YAML schema mediatek,ufs-phy.yaml > > > > Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> > > --- > > v2: fix binding check warning of reg in example > > --- > > .../display/mediatek/mediatek,hdmi.txt | 17 +--- > > .../bindings/phy/mediatek,hdmi-phy.yaml | 90 +++++++++++++++++++ > > 2 files changed, 91 insertions(+), 16 deletions(-) > > create mode 100644 Documentation/devicetree/bindings/phy/mediatek,hdmi-phy.yaml > > > > diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,hdmi.txt b/Documentation/devicetree/bindings/display/mediatek/mediatek,hdmi.txt > > index 7b124242b0c5..edac18951a75 100644 > > --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,hdmi.txt > > +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,hdmi.txt > > @@ -50,22 +50,7 @@ Required properties: > > > > HDMI PHY > > ======== > > - > > -The HDMI PHY serializes the HDMI encoder's three channel 10-bit parallel > > -output and drives the HDMI pads. > > - > > -Required properties: > > -- compatible: "mediatek,<chip>-hdmi-phy" > > -- reg: Physical base address and length of the module's registers > > -- clocks: PLL reference clock > > -- clock-names: must contain "pll_ref" > > -- clock-output-names: must be "hdmitx_dig_cts" on mt8173 > > -- #phy-cells: must be <0> > > -- #clock-cells: must be <0> > > - > > -Optional properties: > > -- mediatek,ibias: TX DRV bias current for <1.65Gbps, defaults to 0xa > > -- mediatek,ibias_up: TX DRV bias current for >1.65Gbps, defaults to 0x1c > > +See phy/mediatek,hdmi-phy.yaml > > > > Example: > > > > diff --git a/Documentation/devicetree/bindings/phy/mediatek,hdmi-phy.yaml b/Documentation/devicetree/bindings/phy/mediatek,hdmi-phy.yaml > > new file mode 100644 > > index 000000000000..77df50204606 > > --- /dev/null > > +++ b/Documentation/devicetree/bindings/phy/mediatek,hdmi-phy.yaml > > @@ -0,0 +1,90 @@ > > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > > +# Copyright (c) 2020 MediaTek > > +%YAML 1.2 > > +--- > > +$id: http://devicetree.org/schemas/phy/mediatek,hdmi-phy.yaml# > > +$schema: http://devicetree.org/meta-schemas/core.yaml# > > + > > +title: MediaTek High Definition Multimedia Interface (HDMI) PHY binding > > + > > +maintainers: > > + - CK Hu <ck.hu@mediatek.com> > > I think you should remove "CK Hu <ck.hu@mediatek.com>" and add latest > mediatek drm maintainer: Ok, will do it, thanks > > DRM DRIVERS FOR MEDIATEK > M: Chun-Kuang Hu <chunkuang.hu@kernel.org> > M: Philipp Zabel <p.zabel@pengutronix.de> > L: dri-devel@lists.freedesktop.org > S: Supported > F: Documentation/devicetree/bindings/display/mediatek/ > F: drivers/gpu/drm/mediatek/ > > Regards, > CK
On Tue, 13 Oct 2020 16:52:03 +0800, Chunfeng Yun wrote: > Convert HDMI PHY binding to YAML schema mediatek,ufs-phy.yaml > > Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> > --- > v2: fix binding check warning of reg in example > --- > .../display/mediatek/mediatek,hdmi.txt | 17 +--- > .../bindings/phy/mediatek,hdmi-phy.yaml | 90 +++++++++++++++++++ > 2 files changed, 91 insertions(+), 16 deletions(-) > create mode 100644 Documentation/devicetree/bindings/phy/mediatek,hdmi-phy.yaml > Reviewed-by: Rob Herring <robh@kernel.org>
diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,hdmi.txt b/Documentation/devicetree/bindings/display/mediatek/mediatek,hdmi.txt index 7b124242b0c5..edac18951a75 100644 --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,hdmi.txt +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,hdmi.txt @@ -50,22 +50,7 @@ Required properties: HDMI PHY ======== - -The HDMI PHY serializes the HDMI encoder's three channel 10-bit parallel -output and drives the HDMI pads. - -Required properties: -- compatible: "mediatek,<chip>-hdmi-phy" -- reg: Physical base address and length of the module's registers -- clocks: PLL reference clock -- clock-names: must contain "pll_ref" -- clock-output-names: must be "hdmitx_dig_cts" on mt8173 -- #phy-cells: must be <0> -- #clock-cells: must be <0> - -Optional properties: -- mediatek,ibias: TX DRV bias current for <1.65Gbps, defaults to 0xa -- mediatek,ibias_up: TX DRV bias current for >1.65Gbps, defaults to 0x1c +See phy/mediatek,hdmi-phy.yaml Example: diff --git a/Documentation/devicetree/bindings/phy/mediatek,hdmi-phy.yaml b/Documentation/devicetree/bindings/phy/mediatek,hdmi-phy.yaml new file mode 100644 index 000000000000..77df50204606 --- /dev/null +++ b/Documentation/devicetree/bindings/phy/mediatek,hdmi-phy.yaml @@ -0,0 +1,90 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +# Copyright (c) 2020 MediaTek +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/phy/mediatek,hdmi-phy.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: MediaTek High Definition Multimedia Interface (HDMI) PHY binding + +maintainers: + - CK Hu <ck.hu@mediatek.com> + - Chunfeng Yun <chunfeng.yun@mediatek.com> + +description: | + The HDMI PHY serializes the HDMI encoder's three channel 10-bit parallel + output and drives the HDMI pads. + +properties: + $nodename: + pattern: "^hdmi-phy@[0-9a-f]+$" + + compatible: + enum: + - mediatek,mt2701-hdmi-phy + - mediatek,mt8173-hdmi-phy + + reg: + maxItems: 1 + + clocks: + items: + - description: PLL reference clock + + clock-names: + items: + - const: pll_ref + + clock-output-names: + items: + - const: hdmitx_dig_cts + + "#phy-cells": + const: 0 + + "#clock-cells": + const: 0 + + mediatek,ibias: + description: + TX DRV bias current for < 1.65Gbps + $ref: /schemas/types.yaml#/definitions/uint32 + minimum: 0 + maximum: 63 + default: 0xa + + mediatek,ibias_up: + description: + TX DRV bias current for >= 1.65Gbps + $ref: /schemas/types.yaml#/definitions/uint32 + minimum: 0 + maximum: 63 + default: 0x1c + +required: + - compatible + - reg + - clocks + - clock-names + - clock-output-names + - "#phy-cells" + - "#clock-cells" + +additionalProperties: false + +examples: + - | + #include <dt-bindings/clock/mt8173-clk.h> + hdmi_phy: hdmi-phy@10209100 { + compatible = "mediatek,mt8173-hdmi-phy"; + reg = <0x10209100 0x24>; + clocks = <&apmixedsys CLK_APMIXED_HDMI_REF>; + clock-names = "pll_ref"; + clock-output-names = "hdmitx_dig_cts"; + mediatek,ibias = <0xa>; + mediatek,ibias_up = <0x1c>; + #clock-cells = <0>; + #phy-cells = <0>; + }; + +...
Convert HDMI PHY binding to YAML schema mediatek,ufs-phy.yaml Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> --- v2: fix binding check warning of reg in example --- .../display/mediatek/mediatek,hdmi.txt | 17 +--- .../bindings/phy/mediatek,hdmi-phy.yaml | 90 +++++++++++++++++++ 2 files changed, 91 insertions(+), 16 deletions(-) create mode 100644 Documentation/devicetree/bindings/phy/mediatek,hdmi-phy.yaml -- 2.18.0