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[PULL,1/2] target-arm: Fix A64 Neon MLS

Message ID 1395681489-29679-2-git-send-email-peter.maydell@linaro.org
State Accepted
Commit d108609bf9ba160d2e2044ce7d553f691ac96dbd
Headers show

Commit Message

Peter Maydell March 24, 2014, 5:18 p.m. UTC 
The order of operands for the accumulate step in disas_simd_3same_int()
was reversed. This only affected the MLS instruction, since all the
other accumulating instructions in this category perform an addition
rather than a subtraction.

Reported-by: Laurent Desnogues <laurent.desnogues@gmail.com>
Tested-by: Laurent Desnogues <laurent.desnogues@gmail.com>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target-arm/translate-a64.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)
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Patch

diff --git a/target-arm/translate-a64.c b/target-arm/translate-a64.c
index 9f06450..9175e48 100644
--- a/target-arm/translate-a64.c
+++ b/target-arm/translate-a64.c
@@ -8925,7 +8925,7 @@  static void disas_simd_3same_int(DisasContext *s, uint32_t insn)
 
                 genfn = fns[size][is_sub];
                 read_vec_element_i32(s, tcg_op1, rd, pass, MO_32);
-                genfn(tcg_res, tcg_res, tcg_op1);
+                genfn(tcg_res, tcg_op1, tcg_res);
             }
 
             write_vec_element_i32(s, tcg_res, rd, pass, MO_32);