@@ -478,7 +478,9 @@ int ccs_pll_calculate(struct device *dev, const struct ccs_pll_limits *lim,
for (op_pll_fr->pre_pll_clk_div = min_op_pre_pll_clk_div;
op_pll_fr->pre_pll_clk_div <= max_op_pre_pll_clk_div;
- op_pll_fr->pre_pll_clk_div += 2 - (op_pll_fr->pre_pll_clk_div & 1)) {
+ op_pll_fr->pre_pll_clk_div +=
+ (pll->flags & CCS_PLL_FLAG_EXT_IP_PLL_DIVIDER) ? 1 :
+ 2 - (op_pll_fr->pre_pll_clk_div & 1)) {
rval = __ccs_pll_calculate(dev, lim, op_lim_fr, op_lim_bk, pll,
op_pll_fr, op_pll_bk, mul, div);
if (rval)
@@ -25,6 +25,7 @@
/* CCS PLL flags */
#define CCS_PLL_FLAG_LANE_SPEED_MODEL BIT(2)
#define CCS_PLL_FLAG_LINK_DECOUPLED BIT(3)
+#define CCS_PLL_FLAG_EXT_IP_PLL_DIVIDER BIT(4)
/**
* struct ccs_pll_branch_fr - CCS PLL configuration (front)
@@ -3211,6 +3211,9 @@ static int ccs_probe(struct i2c_client *client)
sensor->pll.op_lanes = sensor->pll.csi2.lanes;
}
}
+ if (CCS_LIM(sensor, CLOCK_TREE_PLL_CAPABILITY) &
+ CCS_CLOCK_TREE_PLL_CAPABILITY_EXT_DIVIDER)
+ sensor->pll.flags |= CCS_PLL_FLAG_EXT_IP_PLL_DIVIDER;
sensor->pll.ext_clk_freq_hz = sensor->hwcfg.ext_clk;
sensor->pll.scale_n = CCS_LIM(sensor, SCALER_N_MIN);
CCS allows odd PLL dividers other than 1, granted that the corresponding capability bit is set. Support this both in the PLL calculator and the CCS driver. Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com> --- drivers/media/i2c/ccs-pll.c | 4 +++- drivers/media/i2c/ccs-pll.h | 1 + drivers/media/i2c/ccs/ccs-core.c | 3 +++ 3 files changed, 7 insertions(+), 1 deletion(-)