diff mbox

[1/1] clk: exynos-5420: Fix VPLL lock offset

Message ID 1394681222-27882-1-git-send-email-sachin.kamat@linaro.org
State Accepted
Headers show

Commit Message

Sachin Kamat March 13, 2014, 3:27 a.m. UTC
Set it as per the user manual.

Signed-off-by: Sachin Kamat <sachin.kamat@linaro.org>
---
 drivers/clk/samsung/clk-exynos5420.c |    2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

Comments

Tomasz Figa March 13, 2014, 11:53 a.m. UTC | #1
Hi Sachin,

On 13.03.2014 04:27, Sachin Kamat wrote:
> Set it as per the user manual.
>
> Signed-off-by: Sachin Kamat <sachin.kamat@linaro.org>
> ---
>   drivers/clk/samsung/clk-exynos5420.c |    2 +-
>   1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/clk/samsung/clk-exynos5420.c b/drivers/clk/samsung/clk-exynos5420.c
> index 60b26819bed5..7fd6bea467fd 100644
> --- a/drivers/clk/samsung/clk-exynos5420.c
> +++ b/drivers/clk/samsung/clk-exynos5420.c
> @@ -33,7 +33,7 @@
>   #define RPLL_LOCK		0x10050
>   #define IPLL_LOCK		0x10060
>   #define SPLL_LOCK		0x10070
> -#define VPLL_LOCK		0x10070
> +#define VPLL_LOCK		0x10080
>   #define MPLL_LOCK		0x10090
>   #define CPLL_CON0		0x10120
>   #define DPLL_CON0		0x10128
>

Looks fine. Will queue for 3.15, since ATM there is no support for PLL 
rate setting on Exynos 5420 (no rate tables registered).

Best regards,
Tomasz
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Sachin Kamat March 13, 2014, 2:57 p.m. UTC | #2
On 13 March 2014 17:23, Tomasz Figa <t.figa@samsung.com> wrote:
> Hi Sachin,
>
>
> On 13.03.2014 04:27, Sachin Kamat wrote:
>>
>> Set it as per the user manual.
>>
>> Signed-off-by: Sachin Kamat <sachin.kamat@linaro.org>
>> ---

>
> Looks fine. Will queue for 3.15, since ATM there is no support for PLL rate
> setting on Exynos 5420 (no rate tables registered).

Yes, that is correct. Thanks Tomasz.
Sachin Kamat May 1, 2014, 11:10 a.m. UTC | #3
Hi Tomasz,

On 13 March 2014 20:27, Sachin Kamat <sachin.kamat@linaro.org> wrote:
> On 13 March 2014 17:23, Tomasz Figa <t.figa@samsung.com> wrote:
>> Hi Sachin,
>>
>>
>> On 13.03.2014 04:27, Sachin Kamat wrote:
>>>
>>> Set it as per the user manual.
>>>
>>> Signed-off-by: Sachin Kamat <sachin.kamat@linaro.org>
>>> ---
>
>>
>> Looks fine. Will queue for 3.15, since ATM there is no support for PLL rate
>> setting on Exynos 5420 (no rate tables registered).
>
> Yes, that is correct. Thanks Tomasz.

Looks like this patch hasn't made it to mainline yet.
diff mbox

Patch

diff --git a/drivers/clk/samsung/clk-exynos5420.c b/drivers/clk/samsung/clk-exynos5420.c
index 60b26819bed5..7fd6bea467fd 100644
--- a/drivers/clk/samsung/clk-exynos5420.c
+++ b/drivers/clk/samsung/clk-exynos5420.c
@@ -33,7 +33,7 @@ 
 #define RPLL_LOCK		0x10050
 #define IPLL_LOCK		0x10060
 #define SPLL_LOCK		0x10070
-#define VPLL_LOCK		0x10070
+#define VPLL_LOCK		0x10080
 #define MPLL_LOCK		0x10090
 #define CPLL_CON0		0x10120
 #define DPLL_CON0		0x10128