| Message ID | 1393994786-17098-2-git-send-email-julien.grall@linaro.org |
|---|---|
| State | Accepted, archived |
| Headers | show |
On Wed, 2014-03-05 at 12:46 +0800, Julien Grall wrote: > The function v7_init and the define ACTLR_V7_SMP are Cortex A15/A7 > specific. > > To avoid misuse when new ARMv7 processors will be supported, create one > label per processor type and rename ACTLR_V7_SMP in ACTRL_CAXX_SMP > > --- > Changes in v2: > - Patch added Missing an S-o-b though. You can supply one inline here though, no need to resend. > --- > xen/arch/arm/arm32/proc-v7.S | 12 +++++++----- > xen/include/asm-arm/arm32/processor.h | 2 +- > 2 files changed, 8 insertions(+), 6 deletions(-) > > diff --git a/xen/arch/arm/arm32/proc-v7.S b/xen/arch/arm/arm32/proc-v7.S > index 2c8cb9c..8fb42db 100644 > --- a/xen/arch/arm/arm32/proc-v7.S > +++ b/xen/arch/arm/arm32/proc-v7.S > @@ -20,10 +20,12 @@ > #include <asm/asm_defns.h> > #include <asm/arm32/processor.h> > > -v7_init: > +ca15mp_init: > +ca7mp_init: > +brahma15mp_init: > /* Set up the SMP bit in ACTLR */ > mrc CP32(r0, ACTLR) > - orr r0, r0, #(ACTLR_V7_SMP) /* enable SMP bit */ > + orr r0, r0, #(ACTLR_CAXX_SMP) /* enable SMP bit */ > mcr CP32(r0, ACTLR) > mov pc, lr > > @@ -32,7 +34,7 @@ v7_init: > __v7_ca15mp_proc_info: > .long 0x410FC0F0 /* Cortex-A15 */ > .long 0xFF0FFFF0 /* Mask */ > - .long v7_init > + .long ca15mp_init > .size __v7_ca15mp_proc_info, . - __v7_ca15mp_proc_info > > .section ".init.proc.info", #alloc, #execinstr > @@ -40,7 +42,7 @@ __v7_ca15mp_proc_info: > __v7_ca7mp_proc_info: > .long 0x410FC070 /* Cortex-A7 */ > .long 0xFF0FFFF0 /* Mask */ > - .long v7_init > + .long ca7mp_init > .size __v7_ca7mp_proc_info, . - __v7_ca7mp_proc_info > > .section ".init.proc.info", #alloc, #execinstr > @@ -48,7 +50,7 @@ __v7_ca7mp_proc_info: > __v7_brahma15mp_proc_info: > .long 0x420F00F2 /* Broadcom Brahma-B15 */ > .long 0xFF0FFFFF /* Mask */ > - .long v7_init > + .long brahma15mp_init > .size __v7_brahma15mp_proc_info, . - __v7_brahma15mp_proc_info > > /* > diff --git a/xen/include/asm-arm/arm32/processor.h b/xen/include/asm-arm/arm32/processor.h > index d1b89d0..8a35cee 100644 > --- a/xen/include/asm-arm/arm32/processor.h > +++ b/xen/include/asm-arm/arm32/processor.h > @@ -1,7 +1,7 @@ > #ifndef __ASM_ARM_ARM32_PROCESSOR_H > #define __ASM_ARM_ARM32_PROCESSOR_H > > -#define ACTLR_V7_SMP (1<<6) > +#define ACTLR_CAXX_SMP (1<<6) > > #ifndef __ASSEMBLY__ > /* On stack VCPU state */
On 03/12/2014 02:19 PM, Ian Campbell wrote: > On Wed, 2014-03-05 at 12:46 +0800, Julien Grall wrote: >> The function v7_init and the define ACTLR_V7_SMP are Cortex A15/A7 >> specific. >> >> To avoid misuse when new ARMv7 processors will be supported, create one >> label per processor type and rename ACTLR_V7_SMP in ACTRL_CAXX_SMP >> >> --- >> Changes in v2: >> - Patch added > > Missing an S-o-b though. You can supply one inline here though, no need > to resend. oops, sorry. Signed-off-by: Julien Grall <julien.grall@linaro.org>
diff --git a/xen/arch/arm/arm32/proc-v7.S b/xen/arch/arm/arm32/proc-v7.S index 2c8cb9c..8fb42db 100644 --- a/xen/arch/arm/arm32/proc-v7.S +++ b/xen/arch/arm/arm32/proc-v7.S @@ -20,10 +20,12 @@ #include <asm/asm_defns.h> #include <asm/arm32/processor.h> -v7_init: +ca15mp_init: +ca7mp_init: +brahma15mp_init: /* Set up the SMP bit in ACTLR */ mrc CP32(r0, ACTLR) - orr r0, r0, #(ACTLR_V7_SMP) /* enable SMP bit */ + orr r0, r0, #(ACTLR_CAXX_SMP) /* enable SMP bit */ mcr CP32(r0, ACTLR) mov pc, lr @@ -32,7 +34,7 @@ v7_init: __v7_ca15mp_proc_info: .long 0x410FC0F0 /* Cortex-A15 */ .long 0xFF0FFFF0 /* Mask */ - .long v7_init + .long ca15mp_init .size __v7_ca15mp_proc_info, . - __v7_ca15mp_proc_info .section ".init.proc.info", #alloc, #execinstr @@ -40,7 +42,7 @@ __v7_ca15mp_proc_info: __v7_ca7mp_proc_info: .long 0x410FC070 /* Cortex-A7 */ .long 0xFF0FFFF0 /* Mask */ - .long v7_init + .long ca7mp_init .size __v7_ca7mp_proc_info, . - __v7_ca7mp_proc_info .section ".init.proc.info", #alloc, #execinstr @@ -48,7 +50,7 @@ __v7_ca7mp_proc_info: __v7_brahma15mp_proc_info: .long 0x420F00F2 /* Broadcom Brahma-B15 */ .long 0xFF0FFFFF /* Mask */ - .long v7_init + .long brahma15mp_init .size __v7_brahma15mp_proc_info, . - __v7_brahma15mp_proc_info /* diff --git a/xen/include/asm-arm/arm32/processor.h b/xen/include/asm-arm/arm32/processor.h index d1b89d0..8a35cee 100644 --- a/xen/include/asm-arm/arm32/processor.h +++ b/xen/include/asm-arm/arm32/processor.h @@ -1,7 +1,7 @@ #ifndef __ASM_ARM_ARM32_PROCESSOR_H #define __ASM_ARM_ARM32_PROCESSOR_H -#define ACTLR_V7_SMP (1<<6) +#define ACTLR_CAXX_SMP (1<<6) #ifndef __ASSEMBLY__ /* On stack VCPU state */
The function v7_init and the define ACTLR_V7_SMP are Cortex A15/A7 specific. To avoid misuse when new ARMv7 processors will be supported, create one label per processor type and rename ACTLR_V7_SMP in ACTRL_CAXX_SMP --- Changes in v2: - Patch added --- xen/arch/arm/arm32/proc-v7.S | 12 +++++++----- xen/include/asm-arm/arm32/processor.h | 2 +- 2 files changed, 8 insertions(+), 6 deletions(-)