| Message ID | 20200803090658.10073-1-paul.kocialkowski@bootlin.com |
|---|---|
| State | Accepted |
| Commit | 4c85f628f6639e3e3e0a7788416154f28dfcae4f |
| Headers | show |
| Series | media: ov5640: Correct Bit Div register in clock tree diagram | expand |
diff --git a/drivers/media/i2c/ov5640.c b/drivers/media/i2c/ov5640.c index 854031f0b64a..fe08a45b0426 100644 --- a/drivers/media/i2c/ov5640.c +++ b/drivers/media/i2c/ov5640.c @@ -751,7 +751,7 @@ static int ov5640_mod_reg(struct ov5640_dev *sensor, u16 reg, * +->| PLL Root Div | - reg 0x3037, bit 4 * +-+------------+ * | +---------+ - * +->| Bit Div | - reg 0x3035, bits 0-3 + * +->| Bit Div | - reg 0x3034, bits 0-3 * +-+-------+ * | +-------------+ * +->| SCLK Div | - reg 0x3108, bits 0-1
Although the code is correct and doing the right thing, the clock diagram showed the wrong register for the bit divider, which had me doubting the understanding of the tree. Fix this to avoid doubts in the future. Signed-off-by: Paul Kocialkowski <paul.kocialkowski@bootlin.com> --- drivers/media/i2c/ov5640.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)