@@ -279,21 +279,21 @@ static const struct sun8i_codec_clk_div sun8i_codec_bclk_div[] = {
{ .div = 48, .val = 9 },
{ .div = 64, .val = 10 },
{ .div = 96, .val = 11 },
{ .div = 128, .val = 12 },
{ .div = 192, .val = 13 },
};
static u8 sun8i_codec_get_bclk_div(struct sun8i_codec *scodec,
- unsigned int rate,
- unsigned int word_size)
+ unsigned int lrck_div_order,
+ unsigned int sample_rate)
{
unsigned long clk_rate = clk_get_rate(scodec->clk_module);
- unsigned int div = clk_rate / rate / word_size / 2;
+ unsigned int div = clk_rate / sample_rate >> lrck_div_order;
unsigned int best_val = 0, best_diff = ~0;
int i;
for (i = 0; i < ARRAY_SIZE(sun8i_codec_bclk_div); i++) {
const struct sun8i_codec_clk_div *bdiv = &sun8i_codec_bclk_div[i];
unsigned int diff = abs(bdiv->div - div);
if (diff < best_diff) {
@@ -343,30 +343,31 @@ static int sun8i_codec_hw_params(struct snd_pcm_substream *substream,
default:
return -EINVAL;
}
regmap_update_bits(scodec->regmap, SUN8I_AIF1CLK_CTRL,
SUN8I_AIF1CLK_CTRL_AIF1_WORD_SIZ_MASK,
word_size << SUN8I_AIF1CLK_CTRL_AIF1_WORD_SIZ);
- bclk_div = sun8i_codec_get_bclk_div(scodec, params_rate(params), 16);
- regmap_update_bits(scodec->regmap, SUN8I_AIF1CLK_CTRL,
- SUN8I_AIF1CLK_CTRL_AIF1_BCLK_DIV_MASK,
- bclk_div << SUN8I_AIF1CLK_CTRL_AIF1_BCLK_DIV);
-
/* LRCK divider (BCLK/LRCK ratio) */
lrck_div_order = sun8i_codec_get_lrck_div_order(slots, slot_width);
if (lrck_div_order < 0)
return lrck_div_order;
regmap_update_bits(scodec->regmap, SUN8I_AIF1CLK_CTRL,
SUN8I_AIF1CLK_CTRL_AIF1_LRCK_DIV_MASK,
(lrck_div_order - 4) << SUN8I_AIF1CLK_CTRL_AIF1_LRCK_DIV);
+ /* BCLK divider (SYSCLK/BCLK ratio) */
+ bclk_div = sun8i_codec_get_bclk_div(scodec, lrck_div_order, params_rate(params));
+ regmap_update_bits(scodec->regmap, SUN8I_AIF1CLK_CTRL,
+ SUN8I_AIF1CLK_CTRL_AIF1_BCLK_DIV_MASK,
+ bclk_div << SUN8I_AIF1CLK_CTRL_AIF1_BCLK_DIV);
+
sample_rate = sun8i_codec_get_hw_rate(params);
if (sample_rate < 0)
return sample_rate;
regmap_update_bits(scodec->regmap, SUN8I_SYS_SR_CTRL,
SUN8I_SYS_SR_CTRL_AIF1_FS_MASK,
sample_rate << SUN8I_SYS_SR_CTRL_AIF1_FS);
Previously, the BCLK divisor calculation assumed a power-of-two slot width and exactly two slots. In order to support the TDM slot binding and 20/24-bit word sizes, those assumptions must be removed. Due to hardware limitations, the BCLK/LRCK ratio is not as simple as "slot_width * slots". However, the correct value is already calculated elsewhere in this function, since it must also be programmed into the hardware. Reuse that value to calculate the correct SYSCLK/BCLK divisor. Signed-off-by: Samuel Holland <samuel@sholland.org> --- sound/soc/sunxi/sun8i-codec.c | 17 +++++++++-------- 1 file changed, 9 insertions(+), 8 deletions(-)