diff mbox series

[v2,6/7] target/riscv: Clean up fmv.w.x

Message ID 20200724002807.441147-7-richard.henderson@linaro.org
State New
Headers show
Series target/riscv: NaN-boxing for multiple precison | expand

Commit Message

Richard Henderson July 24, 2020, 12:28 a.m. UTC
From: LIU Zhiwei <zhiwei_liu@c-sky.com>


Use tcg_gen_extu_tl_i64 to avoid the ifdef.

Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>

Message-Id: <20200626205917.4545-7-zhiwei_liu@c-sky.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

---
 target/riscv/insn_trans/trans_rvf.inc.c | 6 +-----
 1 file changed, 1 insertion(+), 5 deletions(-)

-- 
2.25.1

Comments

Chih-Min Chao Aug. 6, 2020, 6:28 a.m. UTC | #1
On Fri, Jul 24, 2020 at 8:28 AM Richard Henderson <
richard.henderson@linaro.org> wrote:

> From: LIU Zhiwei <zhiwei_liu@c-sky.com>

>

> Use tcg_gen_extu_tl_i64 to avoid the ifdef.

>

> Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>

> Message-Id: <20200626205917.4545-7-zhiwei_liu@c-sky.com>

> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

> ---

>  target/riscv/insn_trans/trans_rvf.inc.c | 6 +-----

>  1 file changed, 1 insertion(+), 5 deletions(-)

>

> diff --git a/target/riscv/insn_trans/trans_rvf.inc.c

> b/target/riscv/insn_trans/trans_rvf.inc.c

> index f9a9e0643a..0d04677a02 100644

> --- a/target/riscv/insn_trans/trans_rvf.inc.c

> +++ b/target/riscv/insn_trans/trans_rvf.inc.c

> @@ -406,11 +406,7 @@ static bool trans_fmv_w_x(DisasContext *ctx,

> arg_fmv_w_x *a)

>      TCGv t0 = tcg_temp_new();

>      gen_get_gpr(t0, a->rs1);

>

> -#if defined(TARGET_RISCV64)

> -    tcg_gen_mov_i64(cpu_fpr[a->rd], t0);

> -#else

> -    tcg_gen_extu_i32_i64(cpu_fpr[a->rd], t0);

> -#endif

> +    tcg_gen_extu_tl_i64(cpu_fpr[a->rd], t0);

>      gen_nanbox_s(cpu_fpr[a->rd], cpu_fpr[a->rd]);

>

>      mark_fs_dirty(ctx);

> --

> 2.25.1

>

>

>

Reviewed-by: Chih-Min Chao <chihmin.chao@sifive.com>


Chih-Min Chao
<div dir="ltr"><div dir="ltr"><div><br></div></div><br><div class="gmail_quote"><div dir="ltr" class="gmail_attr">On Fri, Jul 24, 2020 at 8:28 AM Richard Henderson &lt;<a href="mailto:richard.henderson@linaro.org">richard.henderson@linaro.org</a>&gt; wrote:<br></div><blockquote class="gmail_quote" style="margin:0px 0px 0px 0.8ex;border-left:1px solid rgb(204,204,204);padding-left:1ex">From: LIU Zhiwei &lt;<a href="mailto:zhiwei_liu@c-sky.com" target="_blank">zhiwei_liu@c-sky.com</a>&gt;<br>
<br>
Use tcg_gen_extu_tl_i64 to avoid the ifdef.<br>
<br>
Signed-off-by: LIU Zhiwei &lt;<a href="mailto:zhiwei_liu@c-sky.com" target="_blank">zhiwei_liu@c-sky.com</a>&gt;<br>

Message-Id: &lt;<a href="mailto:20200626205917.4545-7-zhiwei_liu@c-sky.com" target="_blank">20200626205917.4545-7-zhiwei_liu@c-sky.com</a>&gt;<br>
Signed-off-by: Richard Henderson &lt;<a href="mailto:richard.henderson@linaro.org" target="_blank">richard.henderson@linaro.org</a>&gt;<br>

---<br>
 target/riscv/insn_trans/trans_rvf.inc.c | 6 +-----<br>
 1 file changed, 1 insertion(+), 5 deletions(-)<br>
<br>
diff --git a/target/riscv/insn_trans/trans_rvf.inc.c b/target/riscv/insn_trans/trans_rvf.inc.c<br>
index f9a9e0643a..0d04677a02 100644<br>
--- a/target/riscv/insn_trans/trans_rvf.inc.c<br>
+++ b/target/riscv/insn_trans/trans_rvf.inc.c<br>
@@ -406,11 +406,7 @@ static bool trans_fmv_w_x(DisasContext *ctx, arg_fmv_w_x *a)<br>
     TCGv t0 = tcg_temp_new();<br>
     gen_get_gpr(t0, a-&gt;rs1);<br>
<br>
-#if defined(TARGET_RISCV64)<br>
-    tcg_gen_mov_i64(cpu_fpr[a-&gt;rd], t0);<br>
-#else<br>
-    tcg_gen_extu_i32_i64(cpu_fpr[a-&gt;rd], t0);<br>
-#endif<br>
+    tcg_gen_extu_tl_i64(cpu_fpr[a-&gt;rd], t0);<br>
     gen_nanbox_s(cpu_fpr[a-&gt;rd], cpu_fpr[a-&gt;rd]);<br>
<br>
     mark_fs_dirty(ctx);<br>
-- <br>
2.25.1<br>
<br>
<br></blockquote><div><br></div><div>Reviewed-by: Chih-Min Chao &lt;<a href="mailto:chihmin.chao@sifive.com">chihmin.chao@sifive.com</a>&gt;</div><div><br></div><div><div dir="ltr" class="gmail_signature"><div dir="ltr"><span style="color:rgb(136,136,136)">Chih-Min Chao</span><div style="color:rgb(136,136,136)"></div></div></div></div><div> </div></div></div>
diff mbox series

Patch

diff --git a/target/riscv/insn_trans/trans_rvf.inc.c b/target/riscv/insn_trans/trans_rvf.inc.c
index f9a9e0643a..0d04677a02 100644
--- a/target/riscv/insn_trans/trans_rvf.inc.c
+++ b/target/riscv/insn_trans/trans_rvf.inc.c
@@ -406,11 +406,7 @@  static bool trans_fmv_w_x(DisasContext *ctx, arg_fmv_w_x *a)
     TCGv t0 = tcg_temp_new();
     gen_get_gpr(t0, a->rs1);
 
-#if defined(TARGET_RISCV64)
-    tcg_gen_mov_i64(cpu_fpr[a->rd], t0);
-#else
-    tcg_gen_extu_i32_i64(cpu_fpr[a->rd], t0);
-#endif
+    tcg_gen_extu_tl_i64(cpu_fpr[a->rd], t0);
     gen_nanbox_s(cpu_fpr[a->rd], cpu_fpr[a->rd]);
 
     mark_fs_dirty(ctx);