diff mbox series

dt-bindings: phy: ti: phy-gmii-sel: convert bindings to json-schema

Message ID 20200721225247.31034-1-grygorii.strashko@ti.com
State Accepted
Commit ec799c0f16b81fb42f974fc28172c084de30a4a5
Headers show
Series dt-bindings: phy: ti: phy-gmii-sel: convert bindings to json-schema | expand

Commit Message

Grygorii Strashko July 21, 2020, 10:52 p.m. UTC 
Convert the CPSW Port's Interface Mode Selection PHY bindings documentation
to json-schema.

Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com>

---
 .../bindings/phy/ti,phy-gmii-sel.yaml         | 104 ++++++++++++++++++
 .../bindings/phy/ti-phy-gmii-sel.txt          |  69 ------------
 2 files changed, 104 insertions(+), 69 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/phy/ti,phy-gmii-sel.yaml
 delete mode 100644 Documentation/devicetree/bindings/phy/ti-phy-gmii-sel.txt

-- 
2.17.1

Comments

Rob Herring (Arm) July 23, 2020, 9:17 p.m. UTC | #1 
On Wed, 22 Jul 2020 01:52:47 +0300, Grygorii Strashko wrote:
> Convert the CPSW Port's Interface Mode Selection PHY bindings documentation

> to json-schema.

> 

> Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com>

> ---

>  .../bindings/phy/ti,phy-gmii-sel.yaml         | 104 ++++++++++++++++++

>  .../bindings/phy/ti-phy-gmii-sel.txt          |  69 ------------

>  2 files changed, 104 insertions(+), 69 deletions(-)

>  create mode 100644 Documentation/devicetree/bindings/phy/ti,phy-gmii-sel.yaml

>  delete mode 100644 Documentation/devicetree/bindings/phy/ti-phy-gmii-sel.txt

> 


Applied, thanks!
diff mbox series

Patch

diff --git a/Documentation/devicetree/bindings/phy/ti,phy-gmii-sel.yaml b/Documentation/devicetree/bindings/phy/ti,phy-gmii-sel.yaml
new file mode 100644
index 000000000000..bcec422d7734
--- /dev/null
+++ b/Documentation/devicetree/bindings/phy/ti,phy-gmii-sel.yaml
@@ -0,0 +1,104 @@ 
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+# Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com/
+%YAML 1.2
+---
+$id: "http://devicetree.org/schemas/phy/ti,phy-gmii-sel.yaml#"
+$schema: "http://devicetree.org/meta-schemas/core.yaml#"
+
+title: CPSW Port's Interface Mode Selection PHY Tree Bindings
+
+maintainers:
+  - Kishon Vijay Abraham I <kishon@ti.com>
+
+description: |
+  TI am335x/am437x/dra7(am5)/dm814x CPSW3G Ethernet Subsystem supports
+  two 10/100/1000 Ethernet ports with selectable G/MII, RMII, and RGMII interfaces.
+  The interface mode is selected by configuring the MII mode selection register(s)
+  (GMII_SEL) in the System Control Module chapter (SCM). GMII_SEL register(s) and
+  bit fields placement in SCM are different between SoCs while fields meaning
+  is the same.
+                                               +--------------+
+        +-------------------------------+      |SCM           |
+        |                     CPSW      |      |  +---------+ |
+        |        +--------------------------------+gmii_sel | |
+        |        |                      |      |  +---------+ |
+        |   +----v---+     +--------+   |      +--------------+
+        |   |Port 1..<--+-->GMII/MII<------->
+        |   |        |  |  |        |   |
+        |   +--------+  |  +--------+   |
+        |               |               |
+        |               |  +--------+   |
+        |               |  | RMII   <------->
+        |               +-->        |   |
+        |               |  +--------+   |
+        |               |               |
+        |               |  +--------+   |
+        |               |  | RGMII  <------->
+        |               +-->        |   |
+        |                  +--------+   |
+        +-------------------------------+
+
+  CPSW Port's Interface Mode Selection PHY describes MII interface mode between
+  CPSW Port and Ethernet PHY which depends on Eth PHY and board configuration.
+  |
+  CPSW Port's Interface Mode Selection PHY device should defined as child device
+  of SCM node (scm_conf) and can be attached to each CPSW port node using standard
+  PHY bindings.
+
+properties:
+  compatible:
+    enum:
+      - ti,am3352-phy-gmii-sel
+      - ti,dra7xx-phy-gmii-sel
+      - ti,am43xx-phy-gmii-sel
+      - ti,dm814-phy-gmii-sel
+      - ti,am654-phy-gmii-sel
+
+  reg:
+    description: Address and length of the register set for the device
+
+  '#phy-cells': true
+
+allOf:
+  - if:
+      properties:
+        compatible:
+          contains:
+            enum:
+              - ti,dra7xx-phy-gmii-sel
+              - ti,dm814-phy-gmii-sel
+              - ti,am654-phy-gmii-sel
+    then:
+      properties:
+        '#phy-cells':
+          const: 1
+          description: CPSW port number (starting from 1)
+  - if:
+      properties:
+        compatible:
+          contains:
+            enum:
+              - ti,am3352-phy-gmii-sel
+              - ti,am43xx-phy-gmii-sel
+    then:
+      properties:
+        '#phy-cells':
+          const: 2
+          description: |
+            - CPSW port number (starting from 1)
+            - RMII refclk mode
+
+required:
+  - compatible
+  - reg
+  - '#phy-cells'
+
+additionalProperties: false
+
+examples:
+  - |
+    phy_gmii_sel: phy-gmii-sel@650 {
+        compatible = "ti,am3352-phy-gmii-sel";
+        reg = <0x650 0x4>;
+        #phy-cells = <2>;
+    };
diff --git a/Documentation/devicetree/bindings/phy/ti-phy-gmii-sel.txt b/Documentation/devicetree/bindings/phy/ti-phy-gmii-sel.txt
deleted file mode 100644
index 83b78c1c0644..000000000000
--- a/Documentation/devicetree/bindings/phy/ti-phy-gmii-sel.txt
+++ /dev/null
@@ -1,69 +0,0 @@ 
-CPSW Port's Interface Mode Selection PHY Tree Bindings
------------------------------------------------
-
-TI am335x/am437x/dra7(am5)/dm814x CPSW3G Ethernet Subsystem supports
-two 10/100/1000 Ethernet ports with selectable G/MII, RMII, and RGMII interfaces.
-The interface mode is selected by configuring the MII mode selection register(s)
-(GMII_SEL) in the System Control Module chapter (SCM). GMII_SEL register(s) and
-bit fields placement in SCM are different between SoCs while fields meaning
-is the same.
-                                               +--------------+
-        +-------------------------------+      |SCM           |
-        |                     CPSW      |      |  +---------+ |
-        |        +--------------------------------+gmii_sel | |
-        |        |                      |      |  +---------+ |
-        |   +----v---+     +--------+   |      +--------------+
-        |   |Port 1..<--+-->GMII/MII<------->
-        |   |        |  |  |        |   |
-        |   +--------+  |  +--------+   |
-        |               |               |
-        |               |  +--------+   |
-        |               |  | RMII   <------->
-        |               +-->        |   |
-        |               |  +--------+   |
-        |               |               |
-        |               |  +--------+   |
-        |               |  | RGMII  <------->
-        |               +-->        |   |
-        |                  +--------+   |
-        +-------------------------------+
-
-CPSW Port's Interface Mode Selection PHY describes MII interface mode between
-CPSW Port and Ethernet PHY which depends on Eth PHY and board configuration.
-
-CPSW Port's Interface Mode Selection PHY device should defined as child device
-of SCM node (scm_conf) and can be attached to each CPSW port node using standard
-PHY bindings (See phy/phy-bindings.txt).
-
-Required properties:
-- compatible		: Should be "ti,am3352-phy-gmii-sel" for am335x platform
-			  "ti,dra7xx-phy-gmii-sel" for dra7xx/am57xx platform
-			  "ti,am43xx-phy-gmii-sel" for am43xx platform
-			  "ti,dm814-phy-gmii-sel" for dm814x platform
-			  "ti,am654-phy-gmii-sel" for AM654x/J721E platform
-- reg			: Address and length of the register set for the device
-- #phy-cells		: must be 2.
-			  cell 1 - CPSW port number (starting from 1)
-			  cell 2 - RMII refclk mode
-
-Examples:
-	phy_gmii_sel: phy-gmii-sel {
-		compatible = "ti,am3352-phy-gmii-sel";
-		reg = <0x650 0x4>;
-		#phy-cells = <2>;
-	};
-
-	mac: ethernet@4a100000 {
-		compatible = "ti,am335x-cpsw","ti,cpsw";
-		...
-
-		cpsw_emac0: slave@4a100200 {
-			...
-			phys = <&phy_gmii_sel 1 1>;
-		};
-
-		cpsw_emac1: slave@4a100300 {
-			...
-			phys = <&phy_gmii_sel 2 1>;
-		};
-	};