diff mbox series

[V2,1/7] driver: ddr: imx: skip ddr_ss_gpr config on imx8mn

Message ID 20200530081012.26573-2-peng.fan@nxp.com
State Accepted
Commit 355c620666c205b55164aeb16f86b775f8c5d1fd
Headers show
Series imx: drivers: ddr: ddr driver update | expand

Commit Message

Peng Fan May 30, 2020, 8:10 a.m. UTC 
From: Jacky Bai <ping.bai at nxp.com>

There is no DDR_SS_GPR0 exits on i.MX8MN, so skip setting
this register on i.MX8MN.

Signed-off-by: Jacky Bai <ping.bai at nxp.com>
Signed-off-by: Peng Fan <peng.fan at nxp.com>
---
 drivers/ddr/imx/imx8m/ddr_init.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)
diff mbox series

Patch

diff --git a/drivers/ddr/imx/imx8m/ddr_init.c b/drivers/ddr/imx/imx8m/ddr_init.c
index af8c1427d2..ba5ae05035 100644
--- a/drivers/ddr/imx/imx8m/ddr_init.c
+++ b/drivers/ddr/imx/imx8m/ddr_init.c
@@ -73,7 +73,7 @@  int ddr_init(struct dram_timing_info *dram_timing)
 
 	/* if ddr type is LPDDR4, do it */
 	tmp = reg32_read(DDRC_MSTR(0));
-	if (tmp & (0x1 << 5))
+	if (tmp & (0x1 << 5) && !is_imx8mn())
 		reg32_write(DDRC_DDR_SS_GPR0, 0x01); /* LPDDR4 mode */
 
 	/* determine the initial boot frequency */