| Message ID | 20200527054210.v2.1.Id58c8292b7bc9a9dc55c21e4f5ad6a1a8000dc99@changeid |
|---|---|
| State | Accepted |
| Commit | 537558b22644851eeae2d2fd2816cddbec2218ba |
| Headers | show |
| Series | [v2,1/4] x86: coral: Correct some FSP-M settings | expand |
On Wed, May 27, 2020 at 7:42 PM Simon Glass <sjg at chromium.org> wrote: > > Some settings were modified slightly in the device-tree conversion. Return > these to their original values. > > Signed-off-by: Simon Glass <sjg at chromium.org> > --- > > Changes in v2: None > > arch/x86/dts/chromebook_coral.dts | 5 +++++ > 1 file changed, 5 insertions(+) > Acked-by: Bin Meng <bmeng.cn at gmail.com>
On Thu, May 28, 2020 at 3:54 PM Bin Meng <bmeng.cn at gmail.com> wrote: > > On Wed, May 27, 2020 at 7:42 PM Simon Glass <sjg at chromium.org> wrote: > > > > Some settings were modified slightly in the device-tree conversion. Return > > these to their original values. > > > > Signed-off-by: Simon Glass <sjg at chromium.org> > > --- > > > > Changes in v2: None > > > > arch/x86/dts/chromebook_coral.dts | 5 +++++ > > 1 file changed, 5 insertions(+) > > > > Acked-by: Bin Meng <bmeng.cn at gmail.com> applied to u-boot-x86, thanks!
diff --git a/arch/x86/dts/chromebook_coral.dts b/arch/x86/dts/chromebook_coral.dts index dea35b73a0..fe0d4dedd7 100644 --- a/arch/x86/dts/chromebook_coral.dts +++ b/arch/x86/dts/chromebook_coral.dts @@ -516,6 +516,11 @@ 20 23 22 21 18 19 16 17 /* DQB[7:15] pins of LPDDR4 module with offset of 16 */ 25 28 30 31 26 27 24 29>; + + fspm,dimm0-spd-address = <0>; + fspm,dimm1-spd-address = <0>; + fspm,skip-cse-rbp = <1>; + fspm,enable-s3-heci2 = <0>; }; &fsp_s {
Some settings were modified slightly in the device-tree conversion. Return these to their original values. Signed-off-by: Simon Glass <sjg at chromium.org> --- Changes in v2: None arch/x86/dts/chromebook_coral.dts | 5 +++++ 1 file changed, 5 insertions(+)