[1/2] mv_ddr: ddr3: Use correct bitmask for read sample delay

From: Chris Packham <chris.packham at alliedtelesis.co.nz>

In the Armada 385 functional spec (MV-S109094-00 Rev. C) the read sample
delay fields are 5 bits wide. Use the correct bitmask of 0x1f when
extracting the value.

Signed-off-by: Chris Packham <chris.packham at alliedtelesis.co.nz>

[upstream https://github.com/MarvellEmbeddedProcessors/mv-ddr-marvell/pull/22]
Signed-off-by: Chris Packham <judge.packham at gmail.com>
---

 drivers/ddr/marvell/a38x/ddr3_training_hw_algo.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

On 27.05.20 03:31, Chris Packham wrote:
> From: Chris Packham <chris.packham at alliedtelesis.co.nz>
> 
> In the Armada 385 functional spec (MV-S109094-00 Rev. C) the read sample
> delay fields are 5 bits wide. Use the correct bitmask of 0x1f when
> extracting the value.
> 
> Signed-off-by: Chris Packham <chris.packham at alliedtelesis.co.nz>
> 
> [upstream https://github.com/MarvellEmbeddedProcessors/mv-ddr-marvell/pull/22]
> Signed-off-by: Chris Packham <judge.packham at gmail.com>
> ---

Reviewed-by: Stefan Roese <sr at denx.de>

Thanks,
Stefan

>   drivers/ddr/marvell/a38x/ddr3_training_hw_algo.c | 2 +-
>   1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/drivers/ddr/marvell/a38x/ddr3_training_hw_algo.c b/drivers/ddr/marvell/a38x/ddr3_training_hw_algo.c
> index df832ac6dce0..ce9a47fc2ce0 100644
> --- a/drivers/ddr/marvell/a38x/ddr3_training_hw_algo.c
> +++ b/drivers/ddr/marvell/a38x/ddr3_training_hw_algo.c
> @@ -11,7 +11,7 @@
>   #define VREF_MAX_INDEX			7
>   #define MAX_VALUE			(1024 - 1)
>   #define MIN_VALUE			(-MAX_VALUE)
> -#define GET_RD_SAMPLE_DELAY(data, cs)	((data >> rd_sample_mask[cs]) & 0xf)
> +#define GET_RD_SAMPLE_DELAY(data, cs)	((data >> rd_sample_mask[cs]) & 0x1f)
>   
>   u32 ca_delay;
>   int ddr3_tip_centr_skip_min_win_check = 0;
> 


Viele Gr??e,
Stefan