| Message ID | 1590512951-1045-5-git-send-email-sagar.kadam@sifive.com |
|---|---|
| State | New |
| Headers | show |
| Series | update clock handler and proper cpu features | expand |
Hi Sagar, >-----Original Message----- >From: Sagar Kadam <sagar.kadam at sifive.com> >Sent: 26 May 2020 22:39 >To: u-boot at lists.denx.de; rick at andestech.com; lukma at denx.de >Cc: jagan at amarulasolutions.com; bmeng.cn at gmail.com; Pragnesh Patel ><pragnesh.patel at sifive.com>; seanga2 at gmail.com; Sagar Kadam ><sagar.kadam at sifive.com> >Subject: [PATCH v2 4/4] riscv: cpu: check and append L1 cache to cpu features > >All cpu cores within FU540-C000 having split I/D caches. >Set the L1 feature bit using the i-cache-size as one of the property from s/L1 feature/L1 cache feature >device tree indicating that L1 cache is present on the cpu core. > >=> cpu detail > 0: cpu at 0 rv64imac > ID = 0, freq = 999.100 MHz: L1 cache > 1: cpu at 1 rv64imafdc > ID = 1, freq = 999.100 MHz: L1 cache, MMU > 2: cpu at 2 rv64imafdc > ID = 2, freq = 999.100 MHz: L1 cache, MMU > 3: cpu at 3 rv64imafdc > ID = 3, freq = 999.100 MHz: L1 cache, MMU > 4: cpu at 4 rv64imafdc > ID = 4, freq = 999.100 MHz: L1 cache, MMU > >Signed-off-by: Sagar Shrikant Kadam <sagar.kadam at sifive.com> Reviewed-by: Pragnesh Patel <Pragnesh.patel at sifive.com>
Hi Pragnesh, > -----Original Message----- > From: Pragnesh Patel <pragnesh.patel at sifive.com> > Sent: Wednesday, May 27, 2020 8:10 PM > To: Sagar Kadam <sagar.kadam at sifive.com>; u-boot at lists.denx.de; > rick at andestech.com; lukma at denx.de > Cc: jagan at amarulasolutions.com; bmeng.cn at gmail.com; > seanga2 at gmail.com > Subject: RE: [PATCH v2 4/4] riscv: cpu: check and append L1 cache to cpu > features > > Hi Sagar, > > >-----Original Message----- > >From: Sagar Kadam <sagar.kadam at sifive.com> > >Sent: 26 May 2020 22:39 > >To: u-boot at lists.denx.de; rick at andestech.com; lukma at denx.de > >Cc: jagan at amarulasolutions.com; bmeng.cn at gmail.com; Pragnesh Patel > ><pragnesh.patel at sifive.com>; seanga2 at gmail.com; Sagar Kadam > ><sagar.kadam at sifive.com> > >Subject: [PATCH v2 4/4] riscv: cpu: check and append L1 cache to cpu > >features > > > >All cpu cores within FU540-C000 having split I/D caches. > >Set the L1 feature bit using the i-cache-size as one of the property > >from > > s/L1 feature/L1 cache feature Ok. Will update > > >device tree indicating that L1 cache is present on the cpu core. > > > >=> cpu detail > > 0: cpu at 0 rv64imac > > ID = 0, freq = 999.100 MHz: L1 cache > > 1: cpu at 1 rv64imafdc > > ID = 1, freq = 999.100 MHz: L1 cache, MMU > > 2: cpu at 2 rv64imafdc > > ID = 2, freq = 999.100 MHz: L1 cache, MMU > > 3: cpu at 3 rv64imafdc > > ID = 3, freq = 999.100 MHz: L1 cache, MMU > > 4: cpu at 4 rv64imafdc > > ID = 4, freq = 999.100 MHz: L1 cache, MMU > > > >Signed-off-by: Sagar Shrikant Kadam <sagar.kadam at sifive.com> > > Reviewed-by: Pragnesh Patel <Pragnesh.patel at sifive.com> Thanks for the review's BR, Sagar Kadam
diff --git a/drivers/cpu/riscv_cpu.c b/drivers/cpu/riscv_cpu.c index 8c4b5e7..ce722cb 100644 --- a/drivers/cpu/riscv_cpu.c +++ b/drivers/cpu/riscv_cpu.c @@ -35,6 +35,7 @@ static int riscv_cpu_get_info(struct udevice *dev, struct cpu_info *info) int ret; struct clk clk; const char *mmu; + u32 split_cache_size; /* Zero out the frequency, in case sizeof(ulong) != sizeof(u32) */ info->cpu_freq = 0; @@ -57,6 +58,11 @@ static int riscv_cpu_get_info(struct udevice *dev, struct cpu_info *info) if (mmu) info->features |= BIT(CPU_FEAT_MMU); + /* check if I/D cache is present */ + ret = dev_read_u32(dev, "i-cache-size", &split_cache_size); + if (!ret) + info->features |= BIT(CPU_FEAT_L1_CACHE); + return 0; }
All cpu cores within FU540-C000 having split I/D caches. Set the L1 feature bit using the i-cache-size as one of the property from device tree indicating that L1 cache is present on the cpu core. => cpu detail 0: cpu at 0 rv64imac ID = 0, freq = 999.100 MHz: L1 cache 1: cpu at 1 rv64imafdc ID = 1, freq = 999.100 MHz: L1 cache, MMU 2: cpu at 2 rv64imafdc ID = 2, freq = 999.100 MHz: L1 cache, MMU 3: cpu at 3 rv64imafdc ID = 3, freq = 999.100 MHz: L1 cache, MMU 4: cpu at 4 rv64imafdc ID = 4, freq = 999.100 MHz: L1 cache, MMU Signed-off-by: Sagar Shrikant Kadam <sagar.kadam at sifive.com> --- drivers/cpu/riscv_cpu.c | 6 ++++++ 1 file changed, 6 insertions(+)