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ARM: imx: ddr: Fill in missing DDRC ZQCTLx on i.MX7

Message ID 20200521231239.171224-1-marex@denx.de
State Accepted
Commit cb82ee25f76757ff07d3d42a10e3432af40e0a64
Headers show
Series ARM: imx: ddr: Fill in missing DDRC ZQCTLx on i.MX7 | expand

Commit Message

Marek Vasut May 21, 2020, 11:12 p.m. UTC 
The iMX7 defines further DDRC ZQCTLx registers, however those were
thus far missing from the list of registers and not programmed. On
systems with LPDDR2 or DDR3, those registers must be programmed with
correct values, otherwise the DRAM may not work. However, existing
systems which worked without programming these registers before are
now setting those registers to 0, which is the default value, so no
functional change there.

Signed-off-by: Marek Vasut <marex at denx.de>
Cc: Fabio Estevam <festevam at gmail.com>
Cc: NXP i.MX U-Boot Team <uboot-imx at nxp.com>
Cc: Peng Fan <peng.fan at nxp.com>
Cc: Stefano Babic <sbabic at denx.de>
---
 arch/arm/include/asm/arch-mx7/mx7-ddr.h | 4 +++-
 arch/arm/mach-imx/mx7/ddr.c             | 1 +
 2 files changed, 4 insertions(+), 1 deletion(-)
diff mbox series

Patch

diff --git a/arch/arm/include/asm/arch-mx7/mx7-ddr.h b/arch/arm/include/asm/arch-mx7/mx7-ddr.h
index 37aaee0ad7..bea5dd8ec5 100644
--- a/arch/arm/include/asm/arch-mx7/mx7-ddr.h
+++ b/arch/arm/include/asm/arch-mx7/mx7-ddr.h
@@ -39,7 +39,9 @@  struct ddrc {
 	u32 dramtmg8;		/* 0x0120 */
 	u32 reserved7[0x17];
 	u32 zqctl0;		/* 0x0180 */
-	u32 reserved8[0x03];
+	u32 zqctl1;		/* 0x0184 */
+	u32 zqctl2;		/* 0x0188 */
+	u32 zqstat;		/* 0x018c */
 	u32 dfitmg0;		/* 0x0190 */
 	u32 dfitmg1;		/* 0x0194 */
 	u32 reserved9[0x02];
diff --git a/arch/arm/mach-imx/mx7/ddr.c b/arch/arm/mach-imx/mx7/ddr.c
index 9713835bf2..9ffd8c6c66 100644
--- a/arch/arm/mach-imx/mx7/ddr.c
+++ b/arch/arm/mach-imx/mx7/ddr.c
@@ -58,6 +58,7 @@  void mx7_dram_cfg(struct ddrc *ddrc_regs_val, struct ddrc_mp *ddrc_mp_val,
 	writel(ddrc_regs_val->dramtmg5, &ddrc_regs->dramtmg5);
 	writel(ddrc_regs_val->dramtmg8, &ddrc_regs->dramtmg8);
 	writel(ddrc_regs_val->zqctl0, &ddrc_regs->zqctl0);
+	writel(ddrc_regs_val->zqctl1, &ddrc_regs->zqctl1);
 	writel(ddrc_regs_val->dfitmg0, &ddrc_regs->dfitmg0);
 	writel(ddrc_regs_val->dfitmg1, &ddrc_regs->dfitmg1);
 	writel(ddrc_regs_val->dfiupd0, &ddrc_regs->dfiupd0);