diff mbox series

[4/5] fpga: zynqpl: Flush dcache only for non-bitstream data

Message ID f4d8e59fc8a1713ca4851e351618a1a997c3ebf2.1589266106.git.michal.simek@xilinx.com
State Accepted
Commit ca0c0e07adf3c3baf3851fc17490a0160398c834
Headers show
Series fpga: zynqpl: Add support for AES engine | expand

Commit Message

Michal Simek May 12, 2020, 6:48 a.m. UTC 
From: T Karthik Reddy <t.karthik.reddy at xilinx.com>

In case of aes decryption destination address range must be flushed
before transferring decrypted data to destination.

Signed-off-by: T Karthik Reddy <t.karthik.reddy at xilinx.com>
Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu at xilinx.com>
Signed-off-by: Michal Simek <michal.simek at xilinx.com>
---

 drivers/fpga/zynqpl.c | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)
diff mbox series

Patch

diff --git a/drivers/fpga/zynqpl.c b/drivers/fpga/zynqpl.c
index a323733ef363..6fc5cf57238e 100644
--- a/drivers/fpga/zynqpl.c
+++ b/drivers/fpga/zynqpl.c
@@ -545,8 +545,9 @@  int zynq_decrypt_load(u32 srcaddr, u32 srclen, u32 dstaddr, u32 dstlen,
 	 * Flush destination address range only if image is not
 	 * bitstream.
 	 */
-	flush_dcache_range((u32)dstaddr, (u32)dstaddr +
-			   roundup(dstlen << 2, ARCH_DMA_MINALIGN));
+	if (bstype == BIT_NONE && dstaddr != 0xFFFFFFFF)
+		flush_dcache_range((u32)dstaddr, (u32)dstaddr +
+				   roundup(dstlen << 2, ARCH_DMA_MINALIGN));
 
 	if (zynq_dma_transfer(srcaddr | 1, srclen, dstaddr | 1, dstlen))
 		return FPGA_FAIL;