diff mbox series

[1/5] fpga: zynqpl: Correct PL bitstream loading sequence for zynqaes

Message ID 9c2a724799cf243beb848dad55328db36d07de65.1589266106.git.michal.simek@xilinx.com
State Accepted
Commit 3427f4d2045729c8995b19407daf91ea9a50e4f8
Headers show
Series fpga: zynqpl: Add support for AES engine | expand

Commit Message

Michal Simek May 12, 2020, 6:48 a.m. UTC 
From: Siva Durga Prasad Paladugu <siva.durga.paladugu at xilinx.com>

Correct the PL bitstream loading sequence for zynqaes command by
clearing the loaded PL bitstream before loading the new encrypted
bitstream using the zynq aes command. This was done by setting
the PROG_B same as in case of fpgaload commands.
This patch fixes the issue of loading the encrypted PL bitstream
onto the PL in which a bitstream has already been loaded
successfully.

Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu at xilinx.com>
Signed-off-by: Michal Simek <michal.simek at xilinx.com>
---

 board/xilinx/zynq/cmds.c | 7 +++++--
 drivers/fpga/zynqpl.c    | 7 ++++---
 include/zynqpl.h         | 3 ++-
 3 files changed, 11 insertions(+), 6 deletions(-)
diff mbox series

Patch

diff --git a/board/xilinx/zynq/cmds.c b/board/xilinx/zynq/cmds.c
index 27d44b760daf..ebefbf22120c 100644
--- a/board/xilinx/zynq/cmds.c
+++ b/board/xilinx/zynq/cmds.c
@@ -396,7 +396,8 @@  static int zynq_verify_image(u32 src_ptr)
 			status = zynq_decrypt_load(part_load_addr,
 						   part_img_len,
 						   part_dst_addr,
-						   part_data_len);
+						   part_data_len,
+						   BIT_NONE);
 			if (status != 0) {
 				printf("DECRYPTION_FAIL\n");
 				return -1;
@@ -435,6 +436,7 @@  static int zynq_decrypt_image(cmd_tbl_t *cmdtp, int flag, int argc,
 	char *endp;
 	u32 srcaddr, srclen, dstaddr, dstlen;
 	int status;
+	u8 imgtype = BIT_NONE;
 
 	if (argc < 5 && argc > cmdtp->maxargs)
 		return CMD_RET_USAGE;
@@ -461,7 +463,8 @@  static int zynq_decrypt_image(cmd_tbl_t *cmdtp, int flag, int argc,
 	if (dstlen % 4)
 		dstlen = roundup(dstlen, 4);
 
-	status = zynq_decrypt_load(srcaddr, srclen >> 2, dstaddr, dstlen >> 2);
+	status = zynq_decrypt_load(srcaddr, srclen >> 2, dstaddr,
+				   dstlen >> 2, imgtype);
 	if (status != 0)
 		return CMD_RET_FAILURE;
 
diff --git a/drivers/fpga/zynqpl.c b/drivers/fpga/zynqpl.c
index 21624f715ba0..90a1f09f15e2 100644
--- a/drivers/fpga/zynqpl.c
+++ b/drivers/fpga/zynqpl.c
@@ -201,7 +201,7 @@  static int zynq_dma_xfer_init(bitstream_type bstype)
 	/* Clear loopback bit */
 	clrbits_le32(&devcfg_base->mctrl, DEVCFG_MCTRL_PCAP_LPBK);
 
-	if (bstype != BIT_PARTIAL) {
+	if (bstype != BIT_PARTIAL && bstype != BIT_NONE) {
 		zynq_slcr_devcfg_disable();
 
 		/* Setting PCFG_PROG_B signal to high */
@@ -508,7 +508,8 @@  struct xilinx_fpga_op zynq_op = {
  * Load the encrypted image from src addr and decrypt the image and
  * place it back the decrypted image into dstaddr.
  */
-int zynq_decrypt_load(u32 srcaddr, u32 srclen, u32 dstaddr, u32 dstlen)
+int zynq_decrypt_load(u32 srcaddr, u32 srclen, u32 dstaddr, u32 dstlen,
+		      u8 bstype)
 {
 	if (srcaddr < SZ_1M || dstaddr < SZ_1M) {
 		printf("%s: src and dst addr should be > 1M\n",
@@ -516,7 +517,7 @@  int zynq_decrypt_load(u32 srcaddr, u32 srclen, u32 dstaddr, u32 dstlen)
 		return FPGA_FAIL;
 	}
 
-	if (zynq_dma_xfer_init(BIT_NONE)) {
+	if (zynq_dma_xfer_init(bstype)) {
 		printf("%s: zynq_dma_xfer_init FAIL\n", __func__);
 		return FPGA_FAIL;
 	}
diff --git a/include/zynqpl.h b/include/zynqpl.h
index 766e6918cd38..d7dc064585ea 100644
--- a/include/zynqpl.h
+++ b/include/zynqpl.h
@@ -12,7 +12,8 @@ 
 #include <xilinx.h>
 
 #ifdef CONFIG_CMD_ZYNQ_AES
-int zynq_decrypt_load(u32 srcaddr, u32 dstaddr, u32 srclen, u32 dstlen);
+int zynq_decrypt_load(u32 srcaddr, u32 dstaddr, u32 srclen, u32 dstlen,
+		      u8 bstype);
 #endif
 
 extern struct xilinx_fpga_op zynq_op;