[v8,19/21] sifive: dts: fu540: Enable L2 Cache in U-Boot

Message ID	20200509143037.26009-20-pragnesh.patel@sifive.com
State	New
Headers	show List-Id: U-Boot discussion <u-boot.lists.denx.de> From: pragnesh.patel at sifive.com (Pragnesh Patel) Date: Sat, 9 May 2020 20:00:34 +0530 Subject: [PATCH v8 19/21] sifive: dts: fu540: Enable L2 Cache in U-Boot In-Reply-To: <20200509143037.26009-1-pragnesh.patel@sifive.com> References: <20200509143037.26009-1-pragnesh.patel@sifive.com> Message-ID: <20200509143037.26009-20-pragnesh.patel@sifive.com>
Series	RISC-V SiFive FU540 support SPL \| expand [v8,00/21] RISC-V SiFive FU540 support SPL [v8,01/21] misc: add driver for the SiFive otp controller [v8,02/21] riscv: sifive: fu540: Use OTP DM driver for serial environment variable [v8,03/21] riscv: Add _image_binary_end for SPL [v8,04/21] lib: Makefile: build crc7.c when CONFIG_MMC_SPI [v8,05/21] riscv: sifive: dts: fu540: Add board -u-boot.dtsi files [v8,06/21] sifive: fu540: add ddr driver [v8,07/21] sifive: dts: fu540: Add DDR controller and phy register settings [v8,08/21] riscv: sifive: dts: fu540: add U-Boot dmc node [v8,09/21] clk: sifive: fu540-prci: Add clock enable and disable ops [v8,10/21] clk: sifive: fu540-prci: Add ddr clock initialization in SPL [v8,11/21] clk: sifive: fu540-prci: Add ehternet clock initialization in SPL [v8,12/21] riscv: dts: sifive: Sync hifive-unleashed-a00 dts from linux [v8,13/21] riscv: cpu: fu540: Add support for cpu fu540 [v8,14/21] riscv: Add place-holder for driver compilation [v8,15/21] riscv: sifive: fu540: add SPL configuration [v8,16/21] sifive: fu540: Add sample SD gpt partition layout [v8,17/21] sifive: fu540: Add U-Boot proper sector start [v8,18/21] configs: fu540: Add config options for U-Boot SPL [v8,19/21] sifive: dts: fu540: Enable L2 Cache in U-Boot [v8,20/21] riscv: sifive: fu540: enable all cache ways from U-Boot proper [v8,21/21] doc: sifive: fu540: Add description for OpenSBI generic platform

Message ID

20200509143037.26009-20-pragnesh.patel@sifive.com

State

New

Headers

List-Id: U-Boot discussion <u-boot.lists.denx.de>
From: pragnesh.patel at sifive.com (Pragnesh Patel)
Date: Sat,  9 May 2020 20:00:34 +0530
Subject: [PATCH v8 19/21] sifive: dts: fu540: Enable L2 Cache in U-Boot
In-Reply-To: <20200509143037.26009-1-pragnesh.patel@sifive.com>
References: <20200509143037.26009-1-pragnesh.patel@sifive.com>
Message-ID: <20200509143037.26009-20-pragnesh.patel@sifive.com>

Series

RISC-V SiFive FU540 support SPL | expand

Add L2 cache node to enable cache ways from U-Boot Signed-off-by: Pragnesh Patel <pragnesh.patel at sifive.com> Reviewed-by: Bin Meng <bmeng.cn at gmail.com> --- arch/riscv/dts/fu540-c000-u-boot.dtsi | 4 ++++ 1 file changed, 4 insertions(+)

Comments

Jagan Teki May 10, 2020, 3:14 p.m. UTC | #1

On Sat, May 9, 2020 at 8:02 PM Pragnesh Patel <pragnesh.patel at sifive.com> wrote:
>
> Add L2 cache node to enable cache ways from U-Boot
>
> Signed-off-by: Pragnesh Patel <pragnesh.patel at sifive.com>
> Reviewed-by: Bin Meng <bmeng.cn at gmail.com>
> ---
>  arch/riscv/dts/fu540-c000-u-boot.dtsi | 4 ++++
>  1 file changed, 4 insertions(+)
>
> diff --git a/arch/riscv/dts/fu540-c000-u-boot.dtsi b/arch/riscv/dts/fu540-c000-u-boot.dtsi
> index fc91a7c987..42e43522ed 100644
> --- a/arch/riscv/dts/fu540-c000-u-boot.dtsi
> +++ b/arch/riscv/dts/fu540-c000-u-boot.dtsi
> @@ -82,3 +82,7 @@
>  &qspi2 {
>         u-boot,dm-spl;
>  };
> +
> +&l2cache {
> +       status = "okay";
> +};

Squash with next commit.

Pragnesh Patel May 11, 2020, 6:06 a.m. UTC | #2

>-----Original Message-----
>From: Jagan Teki <jagan at amarulasolutions.com>
>Sent: 10 May 2020 20:44
>To: Pragnesh Patel <pragnesh.patel at sifive.com>
>Cc: U-Boot-Denx <u-boot at lists.denx.de>; Atish Patra
><atish.patra at wdc.com>; Palmer Dabbelt <palmerdabbelt at google.com>; Bin
>Meng <bmeng.cn at gmail.com>; Paul Walmsley <paul.walmsley at sifive.com>;
>Troy Benjegerdes <troy.benjegerdes at sifive.com>; Anup Patel
><anup.patel at wdc.com>; Sagar Kadam <sagar.kadam at sifive.com>; Rick Chen
><rick at andestech.com>
>Subject: Re: [PATCH v8 19/21] sifive: dts: fu540: Enable L2 Cache in U-Boot
>
>[External Email] Do not click links or attachments unless you recognize the
>sender and know the content is safe
>
>On Sat, May 9, 2020 at 8:02 PM Pragnesh Patel <pragnesh.patel at sifive.com>
>wrote:
>>
>> Add L2 cache node to enable cache ways from U-Boot
>>
>> Signed-off-by: Pragnesh Patel <pragnesh.patel at sifive.com>
>> Reviewed-by: Bin Meng <bmeng.cn at gmail.com>
>> ---
>>  arch/riscv/dts/fu540-c000-u-boot.dtsi | 4 ++++
>>  1 file changed, 4 insertions(+)
>>
>> diff --git a/arch/riscv/dts/fu540-c000-u-boot.dtsi b/arch/riscv/dts/fu540-
>c000-u-boot.dtsi
>> index fc91a7c987..42e43522ed 100644
>> --- a/arch/riscv/dts/fu540-c000-u-boot.dtsi
>> +++ b/arch/riscv/dts/fu540-c000-u-boot.dtsi
>> @@ -82,3 +82,7 @@
>>  &qspi2 {
>>         u-boot,dm-spl;
>>  };
>> +
>> +&l2cache {
>> +       status = "okay";
>> +};
>
>Squash with next commit.

Will update in v9.

diff --git a/arch/riscv/dts/fu540-c000-u-boot.dtsi b/arch/riscv/dts/fu540-c000-u-boot.dtsi
index fc91a7c987..42e43522ed 100644
--- a/arch/riscv/dts/fu540-c000-u-boot.dtsi
+++ b/arch/riscv/dts/fu540-c000-u-boot.dtsi
@@ -82,3 +82,7 @@ 
 &qspi2 {
 	u-boot,dm-spl;
 };
+
+&l2cache {
+	status = "okay";
+};

[v8,19/21] sifive: dts: fu540: Enable L2 Cache in U-Boot

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