| Message ID | 20200509143037.26009-16-pragnesh.patel@sifive.com |
|---|---|
| State | Superseded |
| Headers | show |
| Series | RISC-V SiFive FU540 support SPL | expand |
On Sat, May 9, 2020 at 8:02 PM Pragnesh Patel <pragnesh.patel at sifive.com> wrote: > > Add a support for SPL which will boot from L2 LIM (0x0800_0000) and > then SPL will boot U-Boot FIT image (OpenSBI FW_DYNAMIC + u-boot.bin) > from MMC boot devices. > > SPL related code is leveraged from FSBL > (https://github.com/sifive/freedom-u540-c000-bootloader.git) > > Signed-off-by: Pragnesh Patel <pragnesh.patel at sifive.com> > Reviewed-by: Bin Meng <bmeng.cn at gmail.com> > Tested-by: Bin Meng <bmeng.cn at gmail.com> > --- > arch/riscv/cpu/fu540/Makefile | 4 ++ > arch/riscv/cpu/fu540/spl.c | 23 ++++++ > .../dts/hifive-unleashed-a00-u-boot.dtsi | 5 ++ > arch/riscv/include/asm/arch-fu540/spl.h | 14 ++++ > board/sifive/fu540/Kconfig | 12 +++- > board/sifive/fu540/Makefile | 4 ++ > board/sifive/fu540/fu540.c | 24 +++++++ > board/sifive/fu540/spl.c | 72 +++++++++++++++++++ > include/configs/sifive-fu540.h | 18 +++++ > 9 files changed, 174 insertions(+), 2 deletions(-) > create mode 100644 arch/riscv/cpu/fu540/spl.c > create mode 100644 arch/riscv/include/asm/arch-fu540/spl.h > create mode 100644 board/sifive/fu540/spl.c > > diff --git a/arch/riscv/cpu/fu540/Makefile b/arch/riscv/cpu/fu540/Makefile > index 44700d998c..043fb961a5 100644 > --- a/arch/riscv/cpu/fu540/Makefile > +++ b/arch/riscv/cpu/fu540/Makefile > @@ -3,5 +3,9 @@ > # Copyright (C) 2020 SiFive, Inc > # Pragnesh Patel <pragnesh.patel at sifive.com> > > +ifeq ($(CONFIG_SPL_BUILD),y) > +obj-y += spl.o > +else > obj-y += dram.o > obj-y += cpu.o > +endif > diff --git a/arch/riscv/cpu/fu540/spl.c b/arch/riscv/cpu/fu540/spl.c > new file mode 100644 > index 0000000000..2e05d8a6e2 > --- /dev/null > +++ b/arch/riscv/cpu/fu540/spl.c > @@ -0,0 +1,23 @@ > +// SPDX-License-Identifier: GPL-2.0+ > +/* > + * Copyright (C) 2020 SiFive, Inc > + * Pragnesh Patel <pragnesh.patel at sifive.com> > + */ > + > +#include <common.h> > +#include <dm.h> > + > +int soc_spl_init(void) > +{ > + int ret; > + struct udevice *dev; > + > + /* DDR init */ > + ret = uclass_get_device(UCLASS_RAM, 0, &dev); > + if (ret) { > + debug("DRAM init failed: %d\n", ret); > + return ret; > + } > + > + return 0; > +} > diff --git a/arch/riscv/dts/hifive-unleashed-a00-u-boot.dtsi b/arch/riscv/dts/hifive-unleashed-a00-u-boot.dtsi > index 9787332bf1..37de015de6 100644 > --- a/arch/riscv/dts/hifive-unleashed-a00-u-boot.dtsi > +++ b/arch/riscv/dts/hifive-unleashed-a00-u-boot.dtsi > @@ -4,6 +4,7 @@ > */ > > #include "fu540-c000-u-boot.dtsi" > +#include "fu540-hifive-unleashed-a00-sdram-ddr4.dtsi" > > / { > aliases { > @@ -26,3 +27,7 @@ > u-boot,dm-spl; > }; > }; > + > +&gpio { > + u-boot,dm-spl; > +}; > diff --git a/arch/riscv/include/asm/arch-fu540/spl.h b/arch/riscv/include/asm/arch-fu540/spl.h > new file mode 100644 > index 0000000000..0c188be747 > --- /dev/null > +++ b/arch/riscv/include/asm/arch-fu540/spl.h > @@ -0,0 +1,14 @@ > +/* SPDX-License-Identifier: GPL-2.0+ */ > +/* > + * Copyright (C) 2020 SiFive, Inc. > + * > + * Authors: > + * Pragnesh Patel <pragnesh.patel at sifve.com> > + */ > + > +#ifndef _SPL_SIFIVE_H > +#define _SPL_SIFIVE_H > + > +int soc_spl_init(void); > + > +#endif /* _SPL_SIFIVE_H */ > diff --git a/board/sifive/fu540/Kconfig b/board/sifive/fu540/Kconfig > index d41c305227..4a77a2a37b 100644 > --- a/board/sifive/fu540/Kconfig > +++ b/board/sifive/fu540/Kconfig > @@ -7,18 +7,26 @@ config SYS_VENDOR > default "sifive" > > config SYS_CPU > - default "generic" > + default "fu540" > > config SYS_CONFIG_NAME > default "sifive-fu540" > > config SYS_TEXT_BASE > + default 0x80200000 if SPL > default 0x80000000 if !RISCV_SMODE > default 0x80200000 if RISCV_SMODE > > +config SPL_TEXT_BASE > + default 0x08000000 > + > +config SPL_OPENSBI_LOAD_ADDR > + default 0x80000000 > + > config BOARD_SPECIFIC_OPTIONS # dummy > def_bool y > - select GENERIC_RISCV > + select SIFIVE_FU540 > + select SUPPORT_SPL > select RAM > select SPL_RAM if SPL > imply CMD_DHCP > diff --git a/board/sifive/fu540/Makefile b/board/sifive/fu540/Makefile > index 6e1862c475..b05e2f5807 100644 > --- a/board/sifive/fu540/Makefile > +++ b/board/sifive/fu540/Makefile > @@ -3,3 +3,7 @@ > # Copyright (c) 2019 Western Digital Corporation or its affiliates. > > obj-y += fu540.o > + > +ifdef CONFIG_SPL_BUILD > +obj-y += spl.o > +endif > diff --git a/board/sifive/fu540/fu540.c b/board/sifive/fu540/fu540.c > index 540638c919..d05529a86b 100644 > --- a/board/sifive/fu540/fu540.c > +++ b/board/sifive/fu540/fu540.c > @@ -11,6 +11,7 @@ > #include <linux/delay.h> > #include <linux/io.h> > #include <misc.h> > +#include <spl.h> > > /* > * This define is a value used for error/unknown serial. > @@ -114,3 +115,26 @@ int board_init(void) > > return 0; > } > + > +#ifdef CONFIG_SPL > +void board_boot_order(u32 *spl_boot_list) > +{ > + u8 i; > + u32 boot_devices[] = { > +#ifdef CONFIG_SPL_MMC_SUPPORT > + BOOT_DEVICE_MMC1, > +#endif > + }; > + > + for (i = 0; i < ARRAY_SIZE(boot_devices); i++) > + spl_boot_list[i] = boot_devices[i]; > +} > +#endif Board has static jumpers to set boot mode, so boot order won't be possible so add spl_boot_device by assigning MMC boot device for now. Otherwise, Reviewed-by: Jagan Teki <jagan at amarulasolutions.com>
>-----Original Message----- >From: Jagan Teki <jagan at amarulasolutions.com> >Sent: 11 May 2020 14:30 >To: Pragnesh Patel <pragnesh.patel at sifive.com> >Cc: U-Boot-Denx <u-boot at lists.denx.de>; Atish Patra ><atish.patra at wdc.com>; Palmer Dabbelt <palmerdabbelt at google.com>; Bin >Meng <bmeng.cn at gmail.com>; Paul Walmsley <paul.walmsley at sifive.com>; >Troy Benjegerdes <troy.benjegerdes at sifive.com>; Anup Patel ><anup.patel at wdc.com>; Sagar Kadam <sagar.kadam at sifive.com>; Rick Chen ><rick at andestech.com>; Palmer Dabbelt <palmer at sifive.com> >Subject: Re: [PATCH v8 15/21] riscv: sifive: fu540: add SPL configuration > >[External Email] Do not click links or attachments unless you recognize the >sender and know the content is safe > >On Sat, May 9, 2020 at 8:02 PM Pragnesh Patel <pragnesh.patel at sifive.com> >wrote: >> >> Add a support for SPL which will boot from L2 LIM (0x0800_0000) and >> then SPL will boot U-Boot FIT image (OpenSBI FW_DYNAMIC + u-boot.bin) >> from MMC boot devices. >> >> SPL related code is leveraged from FSBL >> (https://github.com/sifive/freedom-u540-c000-bootloader.git) >> >> Signed-off-by: Pragnesh Patel <pragnesh.patel at sifive.com> >> Reviewed-by: Bin Meng <bmeng.cn at gmail.com> >> Tested-by: Bin Meng <bmeng.cn at gmail.com> >> --- >> arch/riscv/cpu/fu540/Makefile | 4 ++ >> arch/riscv/cpu/fu540/spl.c | 23 ++++++ >> .../dts/hifive-unleashed-a00-u-boot.dtsi | 5 ++ >> arch/riscv/include/asm/arch-fu540/spl.h | 14 ++++ >> board/sifive/fu540/Kconfig | 12 +++- >> board/sifive/fu540/Makefile | 4 ++ >> board/sifive/fu540/fu540.c | 24 +++++++ >> board/sifive/fu540/spl.c | 72 +++++++++++++++++++ >> include/configs/sifive-fu540.h | 18 +++++ >> 9 files changed, 174 insertions(+), 2 deletions(-) create mode >> 100644 arch/riscv/cpu/fu540/spl.c create mode 100644 >> arch/riscv/include/asm/arch-fu540/spl.h >> create mode 100644 board/sifive/fu540/spl.c >> >> diff --git a/arch/riscv/cpu/fu540/Makefile >> b/arch/riscv/cpu/fu540/Makefile index 44700d998c..043fb961a5 100644 >> --- a/arch/riscv/cpu/fu540/Makefile >> +++ b/arch/riscv/cpu/fu540/Makefile >> @@ -3,5 +3,9 @@ >> # Copyright (C) 2020 SiFive, Inc >> # Pragnesh Patel <pragnesh.patel at sifive.com> >> >> +ifeq ($(CONFIG_SPL_BUILD),y) >> +obj-y += spl.o >> +else >> obj-y += dram.o >> obj-y += cpu.o >> +endif >> diff --git a/arch/riscv/cpu/fu540/spl.c b/arch/riscv/cpu/fu540/spl.c >> new file mode 100644 index 0000000000..2e05d8a6e2 >> --- /dev/null >> +++ b/arch/riscv/cpu/fu540/spl.c >> @@ -0,0 +1,23 @@ >> +// SPDX-License-Identifier: GPL-2.0+ >> +/* >> + * Copyright (C) 2020 SiFive, Inc >> + * Pragnesh Patel <pragnesh.patel at sifive.com> */ >> + >> +#include <common.h> >> +#include <dm.h> >> + >> +int soc_spl_init(void) >> +{ >> + int ret; >> + struct udevice *dev; >> + >> + /* DDR init */ >> + ret = uclass_get_device(UCLASS_RAM, 0, &dev); >> + if (ret) { >> + debug("DRAM init failed: %d\n", ret); >> + return ret; >> + } >> + >> + return 0; >> +} >> diff --git a/arch/riscv/dts/hifive-unleashed-a00-u-boot.dtsi >> b/arch/riscv/dts/hifive-unleashed-a00-u-boot.dtsi >> index 9787332bf1..37de015de6 100644 >> --- a/arch/riscv/dts/hifive-unleashed-a00-u-boot.dtsi >> +++ b/arch/riscv/dts/hifive-unleashed-a00-u-boot.dtsi >> @@ -4,6 +4,7 @@ >> */ >> >> #include "fu540-c000-u-boot.dtsi" >> +#include "fu540-hifive-unleashed-a00-sdram-ddr4.dtsi" >> >> / { >> aliases { >> @@ -26,3 +27,7 @@ >> u-boot,dm-spl; >> }; >> }; >> + >> +&gpio { >> + u-boot,dm-spl; >> +}; >> diff --git a/arch/riscv/include/asm/arch-fu540/spl.h >> b/arch/riscv/include/asm/arch-fu540/spl.h >> new file mode 100644 >> index 0000000000..0c188be747 >> --- /dev/null >> +++ b/arch/riscv/include/asm/arch-fu540/spl.h >> @@ -0,0 +1,14 @@ >> +/* SPDX-License-Identifier: GPL-2.0+ */ >> +/* >> + * Copyright (C) 2020 SiFive, Inc. >> + * >> + * Authors: >> + * Pragnesh Patel <pragnesh.patel at sifve.com> >> + */ >> + >> +#ifndef _SPL_SIFIVE_H >> +#define _SPL_SIFIVE_H >> + >> +int soc_spl_init(void); >> + >> +#endif /* _SPL_SIFIVE_H */ >> diff --git a/board/sifive/fu540/Kconfig b/board/sifive/fu540/Kconfig >> index d41c305227..4a77a2a37b 100644 >> --- a/board/sifive/fu540/Kconfig >> +++ b/board/sifive/fu540/Kconfig >> @@ -7,18 +7,26 @@ config SYS_VENDOR >> default "sifive" >> >> config SYS_CPU >> - default "generic" >> + default "fu540" >> >> config SYS_CONFIG_NAME >> default "sifive-fu540" >> >> config SYS_TEXT_BASE >> + default 0x80200000 if SPL >> default 0x80000000 if !RISCV_SMODE >> default 0x80200000 if RISCV_SMODE >> >> +config SPL_TEXT_BASE >> + default 0x08000000 >> + >> +config SPL_OPENSBI_LOAD_ADDR >> + default 0x80000000 >> + >> config BOARD_SPECIFIC_OPTIONS # dummy >> def_bool y >> - select GENERIC_RISCV >> + select SIFIVE_FU540 >> + select SUPPORT_SPL >> select RAM >> select SPL_RAM if SPL >> imply CMD_DHCP >> diff --git a/board/sifive/fu540/Makefile b/board/sifive/fu540/Makefile >> index 6e1862c475..b05e2f5807 100644 >> --- a/board/sifive/fu540/Makefile >> +++ b/board/sifive/fu540/Makefile >> @@ -3,3 +3,7 @@ >> # Copyright (c) 2019 Western Digital Corporation or its affiliates. >> >> obj-y += fu540.o >> + >> +ifdef CONFIG_SPL_BUILD >> +obj-y += spl.o >> +endif >> diff --git a/board/sifive/fu540/fu540.c b/board/sifive/fu540/fu540.c >> index 540638c919..d05529a86b 100644 >> --- a/board/sifive/fu540/fu540.c >> +++ b/board/sifive/fu540/fu540.c >> @@ -11,6 +11,7 @@ >> #include <linux/delay.h> >> #include <linux/io.h> >> #include <misc.h> >> +#include <spl.h> >> >> /* >> * This define is a value used for error/unknown serial. >> @@ -114,3 +115,26 @@ int board_init(void) >> >> return 0; >> } >> + >> +#ifdef CONFIG_SPL >> +void board_boot_order(u32 *spl_boot_list) { >> + u8 i; >> + u32 boot_devices[] = { >> +#ifdef CONFIG_SPL_MMC_SUPPORT >> + BOOT_DEVICE_MMC1, >> +#endif >> + }; >> + >> + for (i = 0; i < ARRAY_SIZE(boot_devices); i++) >> + spl_boot_list[i] = boot_devices[i]; } #endif > >Board has static jumpers to set boot mode, so boot order won't be possible so >add spl_boot_device by assigning MMC boot device for now. Will update in v9, thanks for the review. > >Otherwise, > >Reviewed-by: Jagan Teki <jagan at amarulasolutions.com>
diff --git a/arch/riscv/cpu/fu540/Makefile b/arch/riscv/cpu/fu540/Makefile index 44700d998c..043fb961a5 100644 --- a/arch/riscv/cpu/fu540/Makefile +++ b/arch/riscv/cpu/fu540/Makefile @@ -3,5 +3,9 @@ # Copyright (C) 2020 SiFive, Inc # Pragnesh Patel <pragnesh.patel at sifive.com> +ifeq ($(CONFIG_SPL_BUILD),y) +obj-y += spl.o +else obj-y += dram.o obj-y += cpu.o +endif diff --git a/arch/riscv/cpu/fu540/spl.c b/arch/riscv/cpu/fu540/spl.c new file mode 100644 index 0000000000..2e05d8a6e2 --- /dev/null +++ b/arch/riscv/cpu/fu540/spl.c @@ -0,0 +1,23 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2020 SiFive, Inc + * Pragnesh Patel <pragnesh.patel at sifive.com> + */ + +#include <common.h> +#include <dm.h> + +int soc_spl_init(void) +{ + int ret; + struct udevice *dev; + + /* DDR init */ + ret = uclass_get_device(UCLASS_RAM, 0, &dev); + if (ret) { + debug("DRAM init failed: %d\n", ret); + return ret; + } + + return 0; +} diff --git a/arch/riscv/dts/hifive-unleashed-a00-u-boot.dtsi b/arch/riscv/dts/hifive-unleashed-a00-u-boot.dtsi index 9787332bf1..37de015de6 100644 --- a/arch/riscv/dts/hifive-unleashed-a00-u-boot.dtsi +++ b/arch/riscv/dts/hifive-unleashed-a00-u-boot.dtsi @@ -4,6 +4,7 @@ */ #include "fu540-c000-u-boot.dtsi" +#include "fu540-hifive-unleashed-a00-sdram-ddr4.dtsi" / { aliases { @@ -26,3 +27,7 @@ u-boot,dm-spl; }; }; + +&gpio { + u-boot,dm-spl; +}; diff --git a/arch/riscv/include/asm/arch-fu540/spl.h b/arch/riscv/include/asm/arch-fu540/spl.h new file mode 100644 index 0000000000..0c188be747 --- /dev/null +++ b/arch/riscv/include/asm/arch-fu540/spl.h @@ -0,0 +1,14 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2020 SiFive, Inc. + * + * Authors: + * Pragnesh Patel <pragnesh.patel at sifve.com> + */ + +#ifndef _SPL_SIFIVE_H +#define _SPL_SIFIVE_H + +int soc_spl_init(void); + +#endif /* _SPL_SIFIVE_H */ diff --git a/board/sifive/fu540/Kconfig b/board/sifive/fu540/Kconfig index d41c305227..4a77a2a37b 100644 --- a/board/sifive/fu540/Kconfig +++ b/board/sifive/fu540/Kconfig @@ -7,18 +7,26 @@ config SYS_VENDOR default "sifive" config SYS_CPU - default "generic" + default "fu540" config SYS_CONFIG_NAME default "sifive-fu540" config SYS_TEXT_BASE + default 0x80200000 if SPL default 0x80000000 if !RISCV_SMODE default 0x80200000 if RISCV_SMODE +config SPL_TEXT_BASE + default 0x08000000 + +config SPL_OPENSBI_LOAD_ADDR + default 0x80000000 + config BOARD_SPECIFIC_OPTIONS # dummy def_bool y - select GENERIC_RISCV + select SIFIVE_FU540 + select SUPPORT_SPL select RAM select SPL_RAM if SPL imply CMD_DHCP diff --git a/board/sifive/fu540/Makefile b/board/sifive/fu540/Makefile index 6e1862c475..b05e2f5807 100644 --- a/board/sifive/fu540/Makefile +++ b/board/sifive/fu540/Makefile @@ -3,3 +3,7 @@ # Copyright (c) 2019 Western Digital Corporation or its affiliates. obj-y += fu540.o + +ifdef CONFIG_SPL_BUILD +obj-y += spl.o +endif diff --git a/board/sifive/fu540/fu540.c b/board/sifive/fu540/fu540.c index 540638c919..d05529a86b 100644 --- a/board/sifive/fu540/fu540.c +++ b/board/sifive/fu540/fu540.c @@ -11,6 +11,7 @@ #include <linux/delay.h> #include <linux/io.h> #include <misc.h> +#include <spl.h> /* * This define is a value used for error/unknown serial. @@ -114,3 +115,26 @@ int board_init(void) return 0; } + +#ifdef CONFIG_SPL +void board_boot_order(u32 *spl_boot_list) +{ + u8 i; + u32 boot_devices[] = { +#ifdef CONFIG_SPL_MMC_SUPPORT + BOOT_DEVICE_MMC1, +#endif + }; + + for (i = 0; i < ARRAY_SIZE(boot_devices); i++) + spl_boot_list[i] = boot_devices[i]; +} +#endif + +#ifdef CONFIG_SPL_LOAD_FIT +int board_fit_config_name_match(const char *name) +{ + /* boot using first FIT config */ + return 0; +} +#endif diff --git a/board/sifive/fu540/spl.c b/board/sifive/fu540/spl.c new file mode 100644 index 0000000000..b3ff6850e3 --- /dev/null +++ b/board/sifive/fu540/spl.c @@ -0,0 +1,72 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (c) 2019 SiFive, Inc + * + * Authors: + * Pragnesh Patel <pragnesh.patel at sifive.com> + */ + +#include <common.h> +#include <spl.h> +#include <misc.h> +#include <asm/gpio.h> +#include <asm/arch/gpio.h> +#include <asm/arch/spl.h> + +#define GEM_PHY_RESET SIFIVE_GENERIC_GPIO_NR(0, 12) + +int init_clk_and_ddr(void) +{ + int ret; + + ret = soc_spl_init(); + if (ret) { + debug("FU540 SPL init failed: %d\n", ret); + return ret; + } + + /* + * GEMGXL init VSC8541 PHY reset sequence; + * leave pull-down active for 2ms + */ + udelay(2000); + ret = gpio_request(GEM_PHY_RESET, "gem_phy_reset"); + if (ret) { + debug("gem_phy_reset gpio request failed: %d\n", ret); + return ret; + } + + /* Set GPIO 12 (PHY NRESET) */ + ret = gpio_direction_output(GEM_PHY_RESET, 1); + if (ret) { + debug("gem_phy_reset gpio direction set failed: %d\n", ret); + return ret; + } + + udelay(1); + + /* Reset PHY again to enter unmanaged mode */ + gpio_set_value(GEM_PHY_RESET, 0); + udelay(1); + gpio_set_value(GEM_PHY_RESET, 1); + mdelay(15); + + return 0; +} + +void board_init_f(ulong dummy) +{ + int ret; + + ret = spl_early_init(); + if (ret) + panic("spl_early_init() failed: %d\n", ret); + + arch_cpu_init_dm(); + + preloader_console_init(); + + ret = init_clk_and_ddr(); + if (ret) + panic("init_clk_and_ddr() failed: %d\n", ret); +} diff --git a/include/configs/sifive-fu540.h b/include/configs/sifive-fu540.h index 2756ed5a77..ef3ae9b650 100644 --- a/include/configs/sifive-fu540.h +++ b/include/configs/sifive-fu540.h @@ -11,6 +11,22 @@ #include <linux/sizes.h> +#ifdef CONFIG_SPL + +#define CONFIG_SPL_MAX_SIZE 0x00100000 +#define CONFIG_SPL_BSS_START_ADDR 0x85000000 +#define CONFIG_SPL_BSS_MAX_SIZE 0x00100000 +#define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SPL_BSS_START_ADDR + \ + CONFIG_SPL_BSS_MAX_SIZE) +#define CONFIG_SYS_SPL_MALLOC_SIZE 0x00100000 + +#define CONFIG_SPL_LOAD_FIT_ADDRESS 0x84000000 + +#define CONFIG_SPL_STACK (0x08000000 + 0x001D0000 - \ + GENERATED_GBL_DATA_SIZE) + +#endif + #define CONFIG_SYS_SDRAM_BASE 0x80000000 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + SZ_2M) @@ -24,6 +40,7 @@ /* Environment options */ +#ifndef CONFIG_SPL_BUILD #define BOOT_TARGET_DEVICES(func) \ func(MMC, mmc, 0) \ func(DHCP, dhcp, na) @@ -43,5 +60,6 @@ #define CONFIG_PREBOOT \ "setenv fdt_addr ${fdtcontroladdr};" \ "fdt addr ${fdtcontroladdr};" +#endif #endif /* __CONFIG_H */