| Message ID | 20200507231052.23706-1-samuel@sholland.org |
|---|---|
| State | Accepted |
| Commit | abdbefba2a4e9666f798de13b4b88021f23b19f3 |
| Headers | show |
| Series | [1/3] net: sun8i_emac: Use consistent clock bitfield definitions | expand |
diff --git a/drivers/net/sun8i_emac.c b/drivers/net/sun8i_emac.c index 1ae776b446..dcd18833a2 100644 --- a/drivers/net/sun8i_emac.c +++ b/drivers/net/sun8i_emac.c @@ -296,9 +296,9 @@ static int sun8i_emac_set_syscon(struct sun8i_eth_pdata *pdata, if (priv->variant == R40_GMAC) { /* Select RGMII for R40 */ reg = readl(priv->sysctl_reg + 0x164); - reg |= CCM_GMAC_CTRL_TX_CLK_SRC_INT_RGMII | - CCM_GMAC_CTRL_GPIT_RGMII | - CCM_GMAC_CTRL_TX_CLK_DELAY(CONFIG_GMAC_TX_DELAY); + reg |= SC_ETCS_INT_GMII | + SC_EPIT | + (CONFIG_GMAC_TX_DELAY << SC_ETXDC_OFFSET); writel(reg, priv->sysctl_reg + 0x164); return 0;
While the R40 uses a different register for EMAC clock configuration than other chips, the register has a very similar layout. Reuse the existing bitfield definitions in this file, since they match. This allows the driver to compile on the H6 platform, where the CCM_GMAC_CTRL definitions are not present. Signed-off-by: Samuel Holland <samuel at sholland.org> --- drivers/net/sun8i_emac.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-)