| Message ID | 20200506221159.1298-12-michael@walle.cc |
|---|---|
| State | Accepted |
| Commit | 6333cbb3817ed551cd7d4e92f7359c73ccc567fc |
| Headers | show |
| Series | phy: atheros: dt bindings and cleanup | expand |
On Thu, May 07, 2020 at 12:11:58AM +0200, Michael Walle wrote: > We can configure the clock output in the device tree. Disable the > hardcoded one in here. This is highly board-specific and should have > never been enabled in the PHY driver. > > If bisecting shows that this commit breaks your board it probably > depends on the clock output of your Atheros AR8035 PHY. Please have a > look at doc/device-tree-bindings/net/phy/atheros.txt. You need to set > "clk-out-frequency = <125000000>" because that value was the hardcoded > value until this commit. > > Signed-off-by: Michael Walle <michael at walle.cc> > Acked-by: Joe Hershberger <joe.hershberger at ni.com> Applied to u-boot/master, thanks!
diff --git a/drivers/net/phy/atheros.c b/drivers/net/phy/atheros.c index 3cd301c50e..3142733105 100644 --- a/drivers/net/phy/atheros.c +++ b/drivers/net/phy/atheros.c @@ -38,12 +38,6 @@ #define AR803x_CLK_25M_62_5MHZ_DSP 5 #define AR803x_CLK_25M_125MHZ_PLL 6 #define AR803x_CLK_25M_125MHZ_DSP 7 - -/* AR8035: Select frequency on CLK_25M pin through bits 4:3 */ -#define AR8035_CLK_25M_FREQ_25M (0 | 0) -#define AR8035_CLK_25M_FREQ_50M (0 | BIT(3)) -#define AR8035_CLK_25M_FREQ_62M (BIT(4) | 0) -#define AR8035_CLK_25M_FREQ_125M (BIT(4) | BIT(3)) #define AR8035_CLK_25M_MASK GENMASK(4, 3) #define AR803x_CLK_25M_DR_MASK GENMASK(8, 7) @@ -344,18 +338,11 @@ static int ar8031_config(struct phy_device *phydev) static int ar8035_config(struct phy_device *phydev) { int ret; - int regval; ret = ar803x_of_init(phydev); if (ret < 0) return ret; - /* Configure CLK_25M output clock at 125 MHz */ - regval = phy_read_mmd(phydev, MDIO_MMD_AN, AR803x_CLK_25M_SEL_REG); - regval &= ~AR8035_CLK_25M_MASK; /* No surprises */ - regval |= AR8035_CLK_25M_FREQ_125M; - phy_write_mmd(phydev, MDIO_MMD_AN, AR803x_CLK_25M_SEL_REG, regval); - ret = ar803x_delay_config(phydev); if (ret < 0) return ret;