diff mbox series

rockchip: px30: add -u-boot dtsi for soc

Message ID 20200331073246.25634-1-kever.yang@rock-chips.com
State Accepted
Commit 1e1cb9539fc3925796cd2672646a1d1b90186568
Headers show
Series rockchip: px30: add -u-boot dtsi for soc | expand

Commit Message

Kever Yang March 31, 2020, 7:32 a.m. UTC 
Add soc level -u-boot.dtst so that boards can share the common nodes.

Signed-off-by: Kever Yang <kever.yang at rock-chips.com>
---

 arch/arm/dts/px30-evb-u-boot.dtsi     | 82 +-------------------------
 arch/arm/dts/px30-firefly-u-boot.dtsi | 82 +-------------------------
 arch/arm/dts/px30-u-boot.dtsi         | 84 +++++++++++++++++++++++++++
 3 files changed, 88 insertions(+), 160 deletions(-)
 create mode 100644 arch/arm/dts/px30-u-boot.dtsi
diff mbox series

Patch

diff --git a/arch/arm/dts/px30-evb-u-boot.dtsi b/arch/arm/dts/px30-evb-u-boot.dtsi
index a2a2c07dcc..aea9f4d6e5 100644
--- a/arch/arm/dts/px30-evb-u-boot.dtsi
+++ b/arch/arm/dts/px30-evb-u-boot.dtsi
@@ -1,84 +1,6 @@ 
 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
 /*
- * (C) Copyright 2017 Rockchip Electronics Co., Ltd
+ * (C) Copyright 2020 Rockchip Electronics Co., Ltd
  */
 
-/ {
-	aliases {
-		mmc0 = &emmc;
-		mmc1 = &sdmmc;
-	};
-
-	chosen {
-		u-boot,spl-boot-order = &emmc, &sdmmc;
-	};
-};
-
-&dmc {
-	u-boot,dm-pre-reloc;
-};
-
-&uart2 {
-	clock-frequency = <24000000>;
-	u-boot,dm-pre-reloc;
-};
-
-&uart5 {
-	clock-frequency = <24000000>;
-	u-boot,dm-pre-reloc;
-};
-
-&sdmmc {
-	u-boot,dm-pre-reloc;
-
-	/* mmc to sram can't do dma, prevent aborts transfering TF-A parts */
-	u-boot,spl-fifo-mode;
-};
-
-&emmc {
-	u-boot,dm-pre-reloc;
-
-	/* mmc to sram can't do dma, prevent aborts transfering TF-A parts */
-	u-boot,spl-fifo-mode;
-};
-
-&grf {
-	u-boot,dm-pre-reloc;
-};
-
-&pmugrf {
-	u-boot,dm-pre-reloc;
-};
-
-&xin24m {
-	u-boot,dm-pre-reloc;
-};
-
-&cru {
-	u-boot,dm-pre-reloc;
-};
-
-&pmucru {
-	u-boot,dm-pre-reloc;
-};
-
-&saradc {
-	u-boot,dm-pre-reloc;
-	status = "okay";
-};
-
-&gpio0 {
-	u-boot,dm-pre-reloc;
-};
-
-&gpio1 {
-	u-boot,dm-pre-reloc;
-};
-
-&gpio2 {
-	u-boot,dm-pre-reloc;
-};
-
-&gpio3 {
-	u-boot,dm-pre-reloc;
-};
+#include "px30-u-boot.dtsi"
diff --git a/arch/arm/dts/px30-firefly-u-boot.dtsi b/arch/arm/dts/px30-firefly-u-boot.dtsi
index bb782b4e2d..aea9f4d6e5 100644
--- a/arch/arm/dts/px30-firefly-u-boot.dtsi
+++ b/arch/arm/dts/px30-firefly-u-boot.dtsi
@@ -1,84 +1,6 @@ 
 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
 /*
- * (C) Copyright 2019 Rockchip Electronics Co., Ltd
+ * (C) Copyright 2020 Rockchip Electronics Co., Ltd
  */
 
-/ {
-	aliases {
-		mmc0 = &emmc;
-		mmc1 = &sdmmc;
-	};
-
-	chosen {
-		u-boot,spl-boot-order = &emmc, &sdmmc;
-	};
-};
-
-&dmc {
-	u-boot,dm-pre-reloc;
-};
-
-&uart2 {
-	clock-frequency = <24000000>;
-	u-boot,dm-pre-reloc;
-};
-
-&uart5 {
-	clock-frequency = <24000000>;
-	u-boot,dm-pre-reloc;
-};
-
-&sdmmc {
-	u-boot,dm-pre-reloc;
-
-	/* mmc to sram can't do dma, prevent aborts transferring TF-A parts */
-	u-boot,spl-fifo-mode;
-};
-
-&emmc {
-	u-boot,dm-pre-reloc;
-
-	/* mmc to sram can't do dma, prevent aborts transferring TF-A parts */
-	u-boot,spl-fifo-mode;
-};
-
-&grf {
-	u-boot,dm-pre-reloc;
-};
-
-&pmugrf {
-	u-boot,dm-pre-reloc;
-};
-
-&xin24m {
-	u-boot,dm-pre-reloc;
-};
-
-&cru {
-	u-boot,dm-pre-reloc;
-};
-
-&pmucru {
-	u-boot,dm-pre-reloc;
-};
-
-&saradc {
-	u-boot,dm-pre-reloc;
-	status = "okay";
-};
-
-&gpio0 {
-	u-boot,dm-pre-reloc;
-};
-
-&gpio1 {
-	u-boot,dm-pre-reloc;
-};
-
-&gpio2 {
-	u-boot,dm-pre-reloc;
-};
-
-&gpio3 {
-	u-boot,dm-pre-reloc;
-};
+#include "px30-u-boot.dtsi"
diff --git a/arch/arm/dts/px30-u-boot.dtsi b/arch/arm/dts/px30-u-boot.dtsi
new file mode 100644
index 0000000000..bb782b4e2d
--- /dev/null
+++ b/arch/arm/dts/px30-u-boot.dtsi
@@ -0,0 +1,84 @@ 
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * (C) Copyright 2019 Rockchip Electronics Co., Ltd
+ */
+
+/ {
+	aliases {
+		mmc0 = &emmc;
+		mmc1 = &sdmmc;
+	};
+
+	chosen {
+		u-boot,spl-boot-order = &emmc, &sdmmc;
+	};
+};
+
+&dmc {
+	u-boot,dm-pre-reloc;
+};
+
+&uart2 {
+	clock-frequency = <24000000>;
+	u-boot,dm-pre-reloc;
+};
+
+&uart5 {
+	clock-frequency = <24000000>;
+	u-boot,dm-pre-reloc;
+};
+
+&sdmmc {
+	u-boot,dm-pre-reloc;
+
+	/* mmc to sram can't do dma, prevent aborts transferring TF-A parts */
+	u-boot,spl-fifo-mode;
+};
+
+&emmc {
+	u-boot,dm-pre-reloc;
+
+	/* mmc to sram can't do dma, prevent aborts transferring TF-A parts */
+	u-boot,spl-fifo-mode;
+};
+
+&grf {
+	u-boot,dm-pre-reloc;
+};
+
+&pmugrf {
+	u-boot,dm-pre-reloc;
+};
+
+&xin24m {
+	u-boot,dm-pre-reloc;
+};
+
+&cru {
+	u-boot,dm-pre-reloc;
+};
+
+&pmucru {
+	u-boot,dm-pre-reloc;
+};
+
+&saradc {
+	u-boot,dm-pre-reloc;
+	status = "okay";
+};
+
+&gpio0 {
+	u-boot,dm-pre-reloc;
+};
+
+&gpio1 {
+	u-boot,dm-pre-reloc;
+};
+
+&gpio2 {
+	u-boot,dm-pre-reloc;
+};
+
+&gpio3 {
+	u-boot,dm-pre-reloc;
+};