diff mbox series

[v3,01/29] cpu: Support querying the address width

Message ID 20200330171226.v3.1.I094ecfe5a8a83eabccd2ac9f6dc5f6fccbdcea5f@changeid
State Accepted
Commit 600f584d8191799acc19464c4a07f3056083057a
Headers show
Series dm: Add programmatic generation of ACPI tables (part A) | expand

Commit Message

Simon Glass March 30, 2020, 11:12 p.m. UTC 
Different CPUs may support different address widths, meaning the amount of
memory they can address. Add a property for this to the cpu_info struct.

Signed-off-by: Simon Glass <sjg at chromium.org>
Reviewed-by: Bin Meng <bmeng.cn at gmail.com>
---

Changes in v3: None
Changes in v2: None

 drivers/cpu/cpu_sandbox.c | 1 +
 include/cpu.h             | 2 ++
 test/dm/cpu.c             | 1 +
 3 files changed, 4 insertions(+)
diff mbox series

Patch

diff --git a/drivers/cpu/cpu_sandbox.c b/drivers/cpu/cpu_sandbox.c
index ff87e8adca3..05b384f6a45 100644
--- a/drivers/cpu/cpu_sandbox.c
+++ b/drivers/cpu/cpu_sandbox.c
@@ -19,6 +19,7 @@  int cpu_sandbox_get_info(struct udevice *dev, struct cpu_info *info)
 {
 	info->cpu_freq = 42 * 42 * 42 * 42 * 42;
 	info->features = 0x42424242;
+	info->address_width = IS_ENABLED(CONFIG_PHYS_64BIT) ? 64 : 32;
 
 	return 0;
 }
diff --git a/include/cpu.h b/include/cpu.h
index 28dd48feb8f..6b1b6b37b3b 100644
--- a/include/cpu.h
+++ b/include/cpu.h
@@ -44,10 +44,12 @@  enum {
  *
  * @cpu_freq:	Current CPU frequency in Hz
  * @features:	Flags for supported CPU features
+ * @address_width:	Width of the CPU address space in bits (e.g. 32)
  */
 struct cpu_info {
 	ulong cpu_freq;
 	ulong features;
+	uint address_width;
 };
 
 struct cpu_ops {
diff --git a/test/dm/cpu.c b/test/dm/cpu.c
index f5f1caef716..e6dc576ea3c 100644
--- a/test/dm/cpu.c
+++ b/test/dm/cpu.c
@@ -33,6 +33,7 @@  static int dm_test_cpu(struct unit_test_state *uts)
 	ut_assertok(cpu_get_info(dev, &info));
 	ut_asserteq(info.cpu_freq, 42 * 42 * 42 * 42 * 42);
 	ut_asserteq(info.features, 0x42424242);
+	ut_asserteq(info.address_width, 32);
 
 	ut_asserteq(cpu_get_count(dev), 42);