[RFC,v2,07/13] video: add nexell video driver (soc: displaytop)

diff --git a/drivers/video/nexell/soc/s5pxx18_soc_disptop.c b/drivers/video/nexell/soc/s5pxx18_soc_disptop.c
new file mode 100644
index 0000000..626e53a
--- /dev/null
+++ b/drivers/video/nexell/soc/s5pxx18_soc_disptop.c
@@ -0,0 +1,185 @@ 
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2016  Nexell Co., Ltd.
+ *
+ * Author: junghyun, kim <jhkim at nexell.co.kr>
+ */
+
+#include <linux/types.h>
+#include <linux/io.h>
+
+#include "s5pxx18_soc_disptop.h"
+
+static struct {
+	struct nx_disp_top_register_set *pregister;
+} __g_module_variables = { NULL, };
+
+int nx_disp_top_initialize(void)
+{
+	static int binit;
+	u32 i;
+
+	if (binit == 0) {
+		for (i = 0; i < NUMBER_OF_DISPTOP_MODULE; i++)
+			__g_module_variables.pregister = NULL;
+		binit = 1;
+	}
+	return 1;
+}
+
+u32 nx_disp_top_get_number_of_module(void)
+{
+	return NUMBER_OF_DISPTOP_MODULE;
+}
+
+u32 nx_disp_top_get_physical_address(void)
+{
+	static const u32 physical_addr[] = PHY_BASEADDR_DISPTOP_LIST;
+
+	return (u32)(physical_addr[0] + PHY_BASEADDR_DISPLAYTOP_MODULE_OFFSET);
+}
+
+u32 nx_disp_top_get_size_of_register_set(void)
+{
+	return sizeof(struct nx_disp_top_register_set);
+}
+
+void nx_disp_top_set_base_address(void *base_address)
+{
+	__g_module_variables.pregister =
+	    (struct nx_disp_top_register_set *)base_address;
+}
+
+void *nx_disp_top_get_base_address(void)
+{
+	return (void *)__g_module_variables.pregister;
+}
+
+void nx_disp_top_set_resconvmux(int benb, u32 sel)
+{
+	register struct nx_disp_top_register_set *pregister;
+	u32 regvalue;
+
+	pregister = __g_module_variables.pregister;
+	regvalue = (benb << 31) | (sel << 0);
+	writel((u32)regvalue, &pregister->resconv_mux_ctrl);
+}
+
+void nx_disp_top_set_hdmimux(int benb, u32 sel)
+{
+	register struct nx_disp_top_register_set *pregister;
+	u32 regvalue;
+
+	pregister = __g_module_variables.pregister;
+	regvalue = (benb << 31) | (sel << 0);
+	writel((u32)regvalue, &pregister->interconv_mux_ctrl);
+}
+
+void nx_disp_top_set_mipimux(int benb, u32 sel)
+{
+	register struct nx_disp_top_register_set *pregister;
+	u32 regvalue;
+
+	pregister = __g_module_variables.pregister;
+	regvalue = (benb << 31) | (sel << 0);
+	writel((u32)regvalue, &pregister->mipi_mux_ctrl);
+}
+
+void nx_disp_top_set_lvdsmux(int benb, u32 sel)
+{
+	register struct nx_disp_top_register_set *pregister;
+	u32 regvalue;
+
+	pregister = __g_module_variables.pregister;
+	regvalue = (benb << 31) | (sel << 0);
+	writel((u32)regvalue, &pregister->lvds_mux_ctrl);
+}
+
+void nx_disp_top_set_primary_mux(u32 sel)
+{
+	register struct nx_disp_top_register_set *pregister;
+
+	pregister = __g_module_variables.pregister;
+	writel((u32)sel, &pregister->tftmpu_mux);
+}
+
+void nx_disp_top_hdmi_set_vsync_start(u32 sel)
+{
+	register struct nx_disp_top_register_set *pregister;
+
+	pregister = __g_module_variables.pregister;
+	writel((u32)sel, &pregister->hdmisyncctrl0);
+}
+
+void nx_disp_top_hdmi_set_vsync_hsstart_end(u32 start, u32 end)
+{
+	register struct nx_disp_top_register_set *pregister;
+
+	pregister = __g_module_variables.pregister;
+	writel((u32)(end << 16) | (start << 0), &pregister->hdmisyncctrl3);
+}
+
+void nx_disp_top_hdmi_set_hactive_start(u32 sel)
+{
+	register struct nx_disp_top_register_set *pregister;
+
+	pregister = __g_module_variables.pregister;
+	writel((u32)sel, &pregister->hdmisyncctrl1);
+}
+
+void nx_disp_top_hdmi_set_hactive_end(u32 sel)
+{
+	register struct nx_disp_top_register_set *pregister;
+
+	pregister = __g_module_variables.pregister;
+	writel((u32)sel, &pregister->hdmisyncctrl2);
+}
+
+void nx_disp_top_set_hdmifield(u32 enable, u32 init_val, u32 vsynctoggle,
+			       u32 hsynctoggle, u32 vsyncclr, u32 hsyncclr,
+			       u32 field_use, u32 muxsel)
+{
+	register struct nx_disp_top_register_set *pregister;
+	u32 regvalue;
+
+	pregister = __g_module_variables.pregister;
+	regvalue = ((enable & 0x01) << 0) | ((init_val & 0x01) << 1) |
+		   ((vsynctoggle & 0x3fff) << 2) |
+		   ((hsynctoggle & 0x3fff) << 17);
+	writel(regvalue, &pregister->hdmifieldctrl);
+	regvalue = ((field_use & 0x01) << 31) | ((muxsel & 0x01) << 30) |
+		   ((hsyncclr) << 15) | ((vsyncclr) << 0);
+	writel(regvalue, &pregister->greg0);
+}
+
+void nx_disp_top_set_padclock(u32 mux_index, u32 padclk_cfg)
+{
+	register struct nx_disp_top_register_set *pregister;
+	u32 regvalue;
+
+	pregister = __g_module_variables.pregister;
+	regvalue = readl(&pregister->greg1);
+	if (padmux_secondary_mlc == mux_index) {
+		regvalue = regvalue & (~(0x7 << 3));
+		regvalue = regvalue | (padclk_cfg << 3);
+	} else if (padmux_resolution_conv == mux_index) {
+		regvalue = regvalue & (~(0x7 << 6));
+		regvalue = regvalue | (padclk_cfg << 6);
+	} else {
+		regvalue = regvalue & (~(0x7 << 0));
+		regvalue = regvalue | (padclk_cfg << 0);
+	}
+	writel(regvalue, &pregister->greg1);
+}
+
+void nx_disp_top_set_lcdif_enb(int enb)
+{
+	register struct nx_disp_top_register_set *pregister;
+	u32 regvalue;
+
+	pregister = __g_module_variables.pregister;
+	regvalue = readl(&pregister->greg1);
+	regvalue = regvalue & (~(0x1 << 9));
+	regvalue = regvalue | ((enb & 0x1) << 9);
+	writel(regvalue, &pregister->greg1);
+}
diff --git a/drivers/video/nexell/soc/s5pxx18_soc_disptop.h b/drivers/video/nexell/soc/s5pxx18_soc_disptop.h
new file mode 100644
index 0000000..c7bf504
--- /dev/null
+++ b/drivers/video/nexell/soc/s5pxx18_soc_disptop.h
@@ -0,0 +1,385 @@ 
+/* SPDX-License-Identifier: GPL-2.0+
+ *
+ * Copyright (C) 2016  Nexell Co., Ltd.
+ *
+ * Author: junghyun, kim <jhkim at nexell.co.kr>
+ */
+
+#ifndef _S5PXX18_SOC_DISPTOP_H_
+#define _S5PXX18_SOC_DISPTOP_H_
+
+#include "s5pxx18_soc_disptype.h"
+
+#define NUMBER_OF_DISPTOP_MODULE	1
+#define PHY_BASEADDR_DISPLAYTOP_MODULE 0xC0100000
+#define	PHY_BASEADDR_DISPTOP_LIST	\
+		{ PHY_BASEADDR_DISPLAYTOP_MODULE }
+
+#define HDMI_ADDR_OFFSET                                                       \
+	(((PHY_BASEADDR_DISPLAYTOP_MODULE / 0x00100000) % 2) ? 0x100000        \
+							     : 0x000000)
+#define OTHER_ADDR_OFFSET                                                      \
+	(((PHY_BASEADDR_DISPLAYTOP_MODULE / 0x00100000) % 2) ? 0x000000        \
+							     : 0x100000)
+#define PHY_BASEADDR_DISPLAYTOP_MODULE_OFFSET (OTHER_ADDR_OFFSET + 0x001000)
+#define PHY_BASEADDR_DUALDISPLAY_MODULE                                        \
+	(PHY_BASEADDR_DISPLAYTOP_MODULE + OTHER_ADDR_OFFSET + 0x002000)
+#define PHY_BASEADDR_RESCONV_MODULE                                            \
+	(PHY_BASEADDR_DISPLAYTOP_MODULE + OTHER_ADDR_OFFSET + 0x003000)
+#define PHY_BASEADDR_LCDINTERFACE_MODULE                                       \
+	(PHY_BASEADDR_DISPLAYTOP_MODULE + OTHER_ADDR_OFFSET + 0x004000)
+#define PHY_BASEADDR_HDMI_MODULE (PHY_BASEADDR_DISPLAYTOP_MODULE + 0x000000)
+#define PHY_BASEADDR_LVDS_MODULE                                               \
+	(PHY_BASEADDR_DISPLAYTOP_MODULE + OTHER_ADDR_OFFSET + 0x00a000)
+
+#define NUMBER_OF_DUALDISPLAY_MODULE 1
+#define INTNUM_OF_DUALDISPLAY_MODULE_PRIMIRQ                                   \
+	INTNUM_OF_DISPLAYTOP_MODULE_DUALDISPLAY_PRIMIRQ
+#define INTNUM_OF_DUALDISPLAY_MODULE_SECONDIRQ                                 \
+	INTNUM_OF_DISPLAYTOP_MODULE_DUALDISPLAY_SECONDIRQ
+#define RESETINDEX_OF_DUALDISPLAY_MODULE_I_NRST                                \
+	RESETINDEX_OF_DISPLAYTOP_MODULE_I_DUALDISPLAY_NRST
+#define PADINDEX_OF_DUALDISPLAY_O_NCS                                          \
+	PADINDEX_OF_DISPLAYTOP_O_DUAL_DISPLAY_PADPRIMVCLK
+#define PADINDEX_OF_DUALDISPLAY_O_NRD                                          \
+	PADINDEX_OF_DISPLAYTOP_O_DUAL_DISPLAY_PRIM_PADN_HSYNC
+#define PADINDEX_OF_DUALDISPLAY_O_RS                                           \
+	PADINDEX_OF_DISPLAYTOP_O_DUAL_DISPLAY_PRIM_PADN_VSYNC
+#define PADINDEX_OF_DUALDISPLAY_O_NWR                                          \
+	PADINDEX_OF_DISPLAYTOP_O_DUAL_DISPLAY_PRIM_PADDE
+#define PADINDEX_OF_DUALDISPLAY_PADPRIMVCLK                                    \
+	PADINDEX_OF_DISPLAYTOP_O_DUAL_DISPLAY_PADPRIMVCLK
+#define PADINDEX_OF_DUALDISPLAY_O_PRIM_PADN_HSYNC                              \
+	PADINDEX_OF_DISPLAYTOP_O_DUAL_DISPLAY_PRIM_PADN_HSYNC
+#define PADINDEX_OF_DUALDISPLAY_O_PRIM_PADN_VSYNC                              \
+	PADINDEX_OF_DISPLAYTOP_O_DUAL_DISPLAY_PRIM_PADN_VSYNC
+#define PADINDEX_OF_DUALDISPLAY_O_PRIM_PADDE                                   \
+	PADINDEX_OF_DISPLAYTOP_O_DUAL_DISPLAY_PRIM_PADDE
+#define PADINDEX_OF_DUALDISPLAY_PRIM_0_                                        \
+	PADINDEX_OF_DISPLAYTOP_DUAL_DISPLAY_PRIM_0_
+#define PADINDEX_OF_DUALDISPLAY_PRIM_1_                                        \
+	PADINDEX_OF_DISPLAYTOP_DUAL_DISPLAY_PRIM_1_
+#define PADINDEX_OF_DUALDISPLAY_PRIM_2_                                        \
+	PADINDEX_OF_DISPLAYTOP_DUAL_DISPLAY_PRIM_2_
+#define PADINDEX_OF_DUALDISPLAY_PRIM_3_                                        \
+	PADINDEX_OF_DISPLAYTOP_DUAL_DISPLAY_PRIM_3_
+#define PADINDEX_OF_DUALDISPLAY_PRIM_4_                                        \
+	PADINDEX_OF_DISPLAYTOP_DUAL_DISPLAY_PRIM_4_
+#define PADINDEX_OF_DUALDISPLAY_PRIM_5_                                        \
+	PADINDEX_OF_DISPLAYTOP_DUAL_DISPLAY_PRIM_5_
+#define PADINDEX_OF_DUALDISPLAY_PRIM_6_                                        \
+	PADINDEX_OF_DISPLAYTOP_DUAL_DISPLAY_PRIM_6_
+#define PADINDEX_OF_DUALDISPLAY_PRIM_7_                                        \
+	PADINDEX_OF_DISPLAYTOP_DUAL_DISPLAY_PRIM_7_
+#define PADINDEX_OF_DUALDISPLAY_PRIM_8_                                        \
+	PADINDEX_OF_DISPLAYTOP_DUAL_DISPLAY_PRIM_8_
+#define PADINDEX_OF_DUALDISPLAY_PRIM_9_                                        \
+	PADINDEX_OF_DISPLAYTOP_DUAL_DISPLAY_PRIM_9_
+#define PADINDEX_OF_DUALDISPLAY_PRIM_10_                                       \
+	PADINDEX_OF_DISPLAYTOP_DUAL_DISPLAY_PRIM_10_
+#define PADINDEX_OF_DUALDISPLAY_PRIM_11_                                       \
+	PADINDEX_OF_DISPLAYTOP_DUAL_DISPLAY_PRIM_11_
+#define PADINDEX_OF_DUALDISPLAY_PRIM_12_                                       \
+	PADINDEX_OF_DISPLAYTOP_DUAL_DISPLAY_PRIM_12_
+#define PADINDEX_OF_DUALDISPLAY_PRIM_13_                                       \
+	PADINDEX_OF_DISPLAYTOP_DUAL_DISPLAY_PRIM_13_
+#define PADINDEX_OF_DUALDISPLAY_PRIM_14_                                       \
+	PADINDEX_OF_DISPLAYTOP_DUAL_DISPLAY_PRIM_14_
+#define PADINDEX_OF_DUALDISPLAY_PRIM_15_                                       \
+	PADINDEX_OF_DISPLAYTOP_DUAL_DISPLAY_PRIM_15_
+#define PADINDEX_OF_DUALDISPLAY_PRIM_16_                                       \
+	PADINDEX_OF_DISPLAYTOP_DUAL_DISPLAY_PRIM_16_
+#define PADINDEX_OF_DUALDISPLAY_PRIM_17_                                       \
+	PADINDEX_OF_DISPLAYTOP_DUAL_DISPLAY_PRIM_17_
+#define PADINDEX_OF_DUALDISPLAY_PRIM_18_                                       \
+	PADINDEX_OF_DISPLAYTOP_DUAL_DISPLAY_PRIM_18_
+#define PADINDEX_OF_DUALDISPLAY_PRIM_19_                                       \
+	PADINDEX_OF_DISPLAYTOP_DUAL_DISPLAY_PRIM_19_
+#define PADINDEX_OF_DUALDISPLAY_PRIM_20_                                       \
+	PADINDEX_OF_DISPLAYTOP_DUAL_DISPLAY_PRIM_20_
+#define PADINDEX_OF_DUALDISPLAY_PRIM_21_                                       \
+	PADINDEX_OF_DISPLAYTOP_DUAL_DISPLAY_PRIM_21_
+#define PADINDEX_OF_DUALDISPLAY_PRIM_22_                                       \
+	PADINDEX_OF_DISPLAYTOP_DUAL_DISPLAY_PRIM_22_
+#define PADINDEX_OF_DUALDISPLAY_PRIM_23_                                       \
+	PADINDEX_OF_DISPLAYTOP_DUAL_DISPLAY_PRIM_23_
+#define PADINDEX_OF_DUALDISPLAY_PADSECONDVCLK                                  \
+	PADINDEX_OF_DISPLAYTOP_O_DUAL_DISPLAY_PADPRIMVCLK
+#define PADINDEX_OF_DUALDISPLAY_O_SECOND_PADN_HSYNC                            \
+	PADINDEX_OF_DISPLAYTOP_O_DUAL_DISPLAY_PRIM_PADN_HSYNC
+#define PADINDEX_OF_DUALDISPLAY_O_SECOND_PADN_VSYNC                            \
+	PADINDEX_OF_DISPLAYTOP_O_DUAL_DISPLAY_PRIM_PADN_VSYNC
+#define PADINDEX_OF_DUALDISPLAY_O_SECOND_PADDE                                 \
+	PADINDEX_OF_DISPLAYTOP_O_DUAL_DISPLAY_PRIM_PADDE
+#define PADINDEX_OF_DUALDISPLAY_SECOND_0_                                      \
+	PADINDEX_OF_DISPLAYTOP_DUAL_DISPLAY_PRIM_0_
+#define PADINDEX_OF_DUALDISPLAY_SECOND_1_                                      \
+	PADINDEX_OF_DISPLAYTOP_DUAL_DISPLAY_PRIM_1_
+#define PADINDEX_OF_DUALDISPLAY_SECOND_2_                                      \
+	PADINDEX_OF_DISPLAYTOP_DUAL_DISPLAY_PRIM_2_
+#define PADINDEX_OF_DUALDISPLAY_SECOND_3_                                      \
+	PADINDEX_OF_DISPLAYTOP_DUAL_DISPLAY_PRIM_3_
+#define PADINDEX_OF_DUALDISPLAY_SECOND_4_                                      \
+	PADINDEX_OF_DISPLAYTOP_DUAL_DISPLAY_PRIM_4_
+#define PADINDEX_OF_DUALDISPLAY_SECOND_5_                                      \
+	PADINDEX_OF_DISPLAYTOP_DUAL_DISPLAY_PRIM_5_
+#define PADINDEX_OF_DUALDISPLAY_SECOND_6_                                      \
+	PADINDEX_OF_DISPLAYTOP_DUAL_DISPLAY_PRIM_6_
+#define PADINDEX_OF_DUALDISPLAY_SECOND_7_                                      \
+	PADINDEX_OF_DISPLAYTOP_DUAL_DISPLAY_PRIM_7_
+#define PADINDEX_OF_DUALDISPLAY_SECOND_8_                                      \
+	PADINDEX_OF_DISPLAYTOP_DUAL_DISPLAY_PRIM_8_
+#define PADINDEX_OF_DUALDISPLAY_SECOND_9_                                      \
+	PADINDEX_OF_DISPLAYTOP_DUAL_DISPLAY_PRIM_9_
+#define PADINDEX_OF_DUALDISPLAY_SECOND_10_                                     \
+	PADINDEX_OF_DISPLAYTOP_DUAL_DISPLAY_PRIM_10_
+#define PADINDEX_OF_DUALDISPLAY_SECOND_11_                                     \
+	PADINDEX_OF_DISPLAYTOP_DUAL_DISPLAY_PRIM_11_
+#define PADINDEX_OF_DUALDISPLAY_SECOND_12_                                     \
+	PADINDEX_OF_DISPLAYTOP_DUAL_DISPLAY_PRIM_12_
+#define PADINDEX_OF_DUALDISPLAY_SECOND_13_                                     \
+	PADINDEX_OF_DISPLAYTOP_DUAL_DISPLAY_PRIM_13_
+#define PADINDEX_OF_DUALDISPLAY_SECOND_14_                                     \
+	PADINDEX_OF_DISPLAYTOP_DUAL_DISPLAY_PRIM_14_
+#define PADINDEX_OF_DUALDISPLAY_SECOND_15_                                     \
+	PADINDEX_OF_DISPLAYTOP_DUAL_DISPLAY_PRIM_15_
+#define PADINDEX_OF_DUALDISPLAY_SECOND_16_                                     \
+	PADINDEX_OF_DISPLAYTOP_DUAL_DISPLAY_PRIM_16_
+#define PADINDEX_OF_DUALDISPLAY_SECOND_17_                                     \
+	PADINDEX_OF_DISPLAYTOP_DUAL_DISPLAY_PRIM_17_
+#define PADINDEX_OF_DUALDISPLAY_SECOND_18_                                     \
+	PADINDEX_OF_DISPLAYTOP_DUAL_DISPLAY_PRIM_18_
+#define PADINDEX_OF_DUALDISPLAY_SECOND_19_                                     \
+	PADINDEX_OF_DISPLAYTOP_DUAL_DISPLAY_PRIM_19_
+#define PADINDEX_OF_DUALDISPLAY_SECOND_20_                                     \
+	PADINDEX_OF_DISPLAYTOP_DUAL_DISPLAY_PRIM_20_
+#define PADINDEX_OF_DUALDISPLAY_SECOND_21_                                     \
+	PADINDEX_OF_DISPLAYTOP_DUAL_DISPLAY_PRIM_21_
+#define PADINDEX_OF_DUALDISPLAY_SECOND_22_                                     \
+	PADINDEX_OF_DISPLAYTOP_DUAL_DISPLAY_PRIM_22_
+#define PADINDEX_OF_DUALDISPLAY_SECOND_23_                                     \
+	PADINDEX_OF_DISPLAYTOP_DUAL_DISPLAY_PRIM_23_
+
+#define NUMBER_OF_RESCONV_MODULE 1
+#define INTNUM_OF_RESCONV_MODULE INTNUM_OF_DISPLAYTOP_MODULE_RESCONV_IRQ
+#define RESETINDEX_OF_RESCONV_MODULE_I_NRST                                    \
+	RESETINDEX_OF_DISPLAYTOP_MODULE_I_RESCONV_NRST
+#define RESETINDEX_OF_RESCONV_MODULE RESETINDEX_OF_RESCONV_MODULE_I_NRST
+#define NUMBER_OF_LCDINTERFACE_MODULE 1
+#define RESETINDEX_OF_LCDINTERFACE_MODULE_I_NRST                               \
+	RESETINDEX_OF_DISPLAYTOP_MODULE_I_LCDIF_NRST
+#define PADINDEX_OF_LCDINTERFACE_O_VCLK                                        \
+	PADINDEX_OF_DISPLAYTOP_O_DUAL_DISPLAY_PADPRIMVCLK
+#define PADINDEX_OF_LCDINTERFACE_O_NHSYNC                                      \
+	PADINDEX_OF_DISPLAYTOP_O_DUAL_DISPLAY_PRIM_PADN_HSYNC
+#define PADINDEX_OF_LCDINTERFACE_O_NVSYNC                                      \
+	PADINDEX_OF_DISPLAYTOP_O_DUAL_DISPLAY_PRIM_PADN_VSYNC
+#define PADINDEX_OF_LCDINTERFACE_O_DE                                          \
+	PADINDEX_OF_DISPLAYTOP_O_DUAL_DISPLAY_PRIM_PADDE
+#define PADINDEX_OF_LCDINTERFACE_RGB24_0_                                      \
+	PADINDEX_OF_DISPLAYTOP_DUAL_DISPLAY_PRIM_0_
+#define PADINDEX_OF_LCDINTERFACE_RGB24_1_                                      \
+	PADINDEX_OF_DISPLAYTOP_DUAL_DISPLAY_PRIM_1_
+#define PADINDEX_OF_LCDINTERFACE_RGB24_2_                                      \
+	PADINDEX_OF_DISPLAYTOP_DUAL_DISPLAY_PRIM_2_
+#define PADINDEX_OF_LCDINTERFACE_RGB24_3_                                      \
+	PADINDEX_OF_DISPLAYTOP_DUAL_DISPLAY_PRIM_3_
+#define PADINDEX_OF_LCDINTERFACE_RGB24_4_                                      \
+	PADINDEX_OF_DISPLAYTOP_DUAL_DISPLAY_PRIM_4_
+#define PADINDEX_OF_LCDINTERFACE_RGB24_5_                                      \
+	PADINDEX_OF_DISPLAYTOP_DUAL_DISPLAY_PRIM_5_
+#define PADINDEX_OF_LCDINTERFACE_RGB24_6_                                      \
+	PADINDEX_OF_DISPLAYTOP_DUAL_DISPLAY_PRIM_6_
+#define PADINDEX_OF_LCDINTERFACE_RGB24_7_                                      \
+	PADINDEX_OF_DISPLAYTOP_DUAL_DISPLAY_PRIM_7_
+#define PADINDEX_OF_LCDINTERFACE_RGB24_8_                                      \
+	PADINDEX_OF_DISPLAYTOP_DUAL_DISPLAY_PRIM_8_
+#define PADINDEX_OF_LCDINTERFACE_RGB24_9_                                      \
+	PADINDEX_OF_DISPLAYTOP_DUAL_DISPLAY_PRIM_9_
+#define PADINDEX_OF_LCDINTERFACE_RGB24_10_                                     \
+	PADINDEX_OF_DISPLAYTOP_DUAL_DISPLAY_PRIM_10_
+#define PADINDEX_OF_LCDINTERFACE_RGB24_11_                                     \
+	PADINDEX_OF_DISPLAYTOP_DUAL_DISPLAY_PRIM_11_
+#define PADINDEX_OF_LCDINTERFACE_RGB24_12_                                     \
+	PADINDEX_OF_DISPLAYTOP_DUAL_DISPLAY_PRIM_12_
+#define PADINDEX_OF_LCDINTERFACE_RGB24_13_                                     \
+	PADINDEX_OF_DISPLAYTOP_DUAL_DISPLAY_PRIM_13_
+#define PADINDEX_OF_LCDINTERFACE_RGB24_14_                                     \
+	PADINDEX_OF_DISPLAYTOP_DUAL_DISPLAY_PRIM_14_
+#define PADINDEX_OF_LCDINTERFACE_RGB24_15_                                     \
+	PADINDEX_OF_DISPLAYTOP_DUAL_DISPLAY_PRIM_15_
+#define PADINDEX_OF_LCDINTERFACE_RGB24_16_                                     \
+	PADINDEX_OF_DISPLAYTOP_DUAL_DISPLAY_PRIM_16_
+#define PADINDEX_OF_LCDINTERFACE_RGB24_17_                                     \
+	PADINDEX_OF_DISPLAYTOP_DUAL_DISPLAY_PRIM_17_
+#define PADINDEX_OF_LCDINTERFACE_RGB24_18_                                     \
+	PADINDEX_OF_DISPLAYTOP_DUAL_DISPLAY_PRIM_18_
+#define PADINDEX_OF_LCDINTERFACE_RGB24_19_                                     \
+	PADINDEX_OF_DISPLAYTOP_DUAL_DISPLAY_PRIM_19_
+#define PADINDEX_OF_LCDINTERFACE_RGB24_20_                                     \
+	PADINDEX_OF_DISPLAYTOP_DUAL_DISPLAY_PRIM_20_
+#define PADINDEX_OF_LCDINTERFACE_RGB24_21_                                     \
+	PADINDEX_OF_DISPLAYTOP_DUAL_DISPLAY_PRIM_21_
+#define PADINDEX_OF_LCDINTERFACE_RGB24_22_                                     \
+	PADINDEX_OF_DISPLAYTOP_DUAL_DISPLAY_PRIM_22_
+#define PADINDEX_OF_LCDINTERFACE_RGB24_23_                                     \
+	PADINDEX_OF_DISPLAYTOP_DUAL_DISPLAY_PRIM_23_
+
+#define NUMBER_OF_HDMI_MODULE 1
+#define INTNUM_OF_HDMI_MODULE INTNUM_OF_DISPLAYTOP_MODULE_HDMI_IRQ
+#define RESETINDEX_OF_HDMI_MODULE_I_NRST                                       \
+	RESETINDEX_OF_DISPLAYTOP_MODULE_I_HDMI_NRST
+#define RESETINDEX_OF_HDMI_MODULE_I_NRST_VIDEO                                 \
+	RESETINDEX_OF_DISPLAYTOP_MODULE_I_HDMI_VIDEO_NRST
+#define RESETINDEX_OF_HDMI_MODULE_I_NRST_SPDIF                                 \
+	RESETINDEX_OF_DISPLAYTOP_MODULE_I_HDMI_SPDIF_NRST
+#define RESETINDEX_OF_HDMI_MODULE_I_NRST_TMDS                                  \
+	RESETINDEX_OF_DISPLAYTOP_MODULE_I_HDMI_TMDS_NRST
+#define RESETINDEX_OF_HDMI_MODULE_I_NRST_PHY                                   \
+	RESETINDEX_OF_DISPLAYTOP_MODULE_I_HDMI_PHY_NRST
+#define PADINDEX_OF_HDMI_I_PHY_CLKI PADINDEX_OF_DISPLAYTOP_I_HDMI_CLKI
+#define PADINDEX_OF_HDMI_O_PHY_CLKO PADINDEX_OF_DISPLAYTOP_O_HDMI_CLKO
+#define PADINDEX_OF_HDMI_IO_PHY_REXT PADINDEX_OF_DISPLAYTOP_IO_HDMI_REXT
+#define PADINDEX_OF_HDMI_O_PHY_TX0P PADINDEX_OF_DISPLAYTOP_O_HDMI_TX0P
+#define PADINDEX_OF_HDMI_O_PHY_TX0N PADINDEX_OF_DISPLAYTOP_O_HDMI_TX0N
+#define PADINDEX_OF_HDMI_O_PHY_TX1P PADINDEX_OF_DISPLAYTOP_O_HDMI_TX1P
+#define PADINDEX_OF_HDMI_O_PHY_TX1N PADINDEX_OF_DISPLAYTOP_O_HDMI_TX1N
+#define PADINDEX_OF_HDMI_O_PHY_TX2P PADINDEX_OF_DISPLAYTOP_O_HDMI_TX2P
+#define PADINDEX_OF_HDMI_O_PHY_TX2N PADINDEX_OF_DISPLAYTOP_O_HDMI_TX2N
+#define PADINDEX_OF_HDMI_O_PHY_TXCP PADINDEX_OF_DISPLAYTOP_O_HDMI_TXCP
+#define PADINDEX_OF_HDMI_O_PHY_TXCN PADINDEX_OF_DISPLAYTOP_O_HDMI_TXCN
+#define PADINDEX_OF_HDMI_I_HOTPLUG PADINDEX_OF_DISPLAYTOP_I_HDMI_HOTPLUG_5V
+#define PADINDEX_OF_HDMI_IO_PAD_CEC PADINDEX_OF_DISPLAYTOP_IO_HDMI_CEC
+#define NUMBER_OF_LVDS_MODULE 1
+
+#define RESETINDEX_OF_LVDS_MODULE_I_RESETN                                     \
+	RESETINDEX_OF_DISPLAYTOP_MODULE_I_LVDS_NRST
+#define RESETINDEX_OF_LVDS_MODULE RESETINDEX_OF_LVDS_MODULE_I_RESETN
+
+#define PADINDEX_OF_LVDS_TAP PADINDEX_OF_DISPLAYTOP_LVDS_TXP_A
+#define PADINDEX_OF_LVDS_TAN PADINDEX_OF_DISPLAYTOP_LVDS_TXN_A
+#define PADINDEX_OF_LVDS_TBP PADINDEX_OF_DISPLAYTOP_LVDS_TXP_B
+#define PADINDEX_OF_LVDS_TBN PADINDEX_OF_DISPLAYTOP_LVDS_TXN_B
+#define PADINDEX_OF_LVDS_TCP PADINDEX_OF_DISPLAYTOP_LVDS_TXP_C
+#define PADINDEX_OF_LVDS_TCN PADINDEX_OF_DISPLAYTOP_LVDS_TXN_C
+#define PADINDEX_OF_LVDS_TDP PADINDEX_OF_DISPLAYTOP_LVDS_TXP_D
+#define PADINDEX_OF_LVDS_TDN PADINDEX_OF_DISPLAYTOP_LVDS_TXN_D
+#define PADINDEX_OF_LVDS_TCLKP PADINDEX_OF_DISPLAYTOP_LVDS_TXP_CLK
+#define PADINDEX_OF_LVDS_TCLKN PADINDEX_OF_DISPLAYTOP_LVDS_TXN_CLK
+#define PADINDEX_OF_LVDS_ROUT PADINDEX_OF_DISPLAYTOP_LVDS_ROUT
+#define PADINDEX_OF_LVDS_TEP PADINDEX_OF_DISPLAYTOP_LVDS_TXN_E
+#define PADINDEX_OF_LVDS_TEN PADINDEX_OF_DISPLAYTOP_LVDS_TXN_E
+#define NUMBER_OF_DISPTOP_CLKGEN_MODULE 5
+
+enum disptop_clkgen_module_index {
+	res_conv_clkgen = 0,
+	lcdif_clkgen = 1,
+	to_mipi_clkgen = 2,
+	to_lvds_clkgen = 3,
+	hdmi_clkgen = 4,
+};
+
+enum disptop_res_conv_iclk_cclk {
+	res_conv_iclk = 0,
+	res_conv_cclk = 1,
+};
+
+enum disptop_res_conv_oclk {
+	res_conv_oclk = 1,
+};
+
+enum disptop_lcdif_clk {
+	lcdif_pixel_clkx_n = 0,
+	lcdif_pixel_clk = 1,
+};
+
+#define HDMI_SPDIF_CLKGEN 2
+#define HDMI_SPDIF_CLKOUT 0
+#define HDMI_I_VCLK_CLKOUT 0
+#define PHY_BASEADDR_DISPTOP_CLKGEN0_MODULE                                    \
+	(PHY_BASEADDR_DISPLAYTOP_MODULE + OTHER_ADDR_OFFSET + 0x006000)
+#define PHY_BASEADDR_DISPTOP_CLKGEN1_MODULE                                    \
+	(PHY_BASEADDR_DISPLAYTOP_MODULE + OTHER_ADDR_OFFSET + 0x007000)
+#define PHY_BASEADDR_DISPTOP_CLKGEN2_MODULE                                    \
+	(PHY_BASEADDR_DISPLAYTOP_MODULE + OTHER_ADDR_OFFSET + 0x005000)
+#define PHY_BASEADDR_DISPTOP_CLKGEN3_MODULE                                    \
+	(PHY_BASEADDR_DISPLAYTOP_MODULE + OTHER_ADDR_OFFSET + 0x008000)
+#define PHY_BASEADDR_DISPTOP_CLKGEN4_MODULE                                    \
+	(PHY_BASEADDR_DISPLAYTOP_MODULE + OTHER_ADDR_OFFSET + 0x009000)
+
+struct nx_disp_top_register_set {
+	u32 resconv_mux_ctrl;
+	u32 interconv_mux_ctrl;
+	u32 mipi_mux_ctrl;
+	u32 lvds_mux_ctrl;
+	u32 hdmifixctrl0;
+	u32 hdmisyncctrl0;
+	u32 hdmisyncctrl1;
+	u32 hdmisyncctrl2;
+	u32 hdmisyncctrl3;
+	u32 tftmpu_mux;
+	u32 hdmifieldctrl;
+	u32 greg0;
+	u32 greg1;
+	u32 greg2;
+	u32 greg3;
+	u32 greg4;
+	u32 greg5;
+};
+
+int nx_disp_top_initialize(void);
+u32 nx_disp_top_get_number_of_module(void);
+
+u32 nx_disp_top_get_physical_address(void);
+u32 nx_disp_top_get_size_of_register_set(void);
+void nx_disp_top_set_base_address(void *base_address);
+void *nx_disp_top_get_base_address(void);
+int nx_disp_top_open_module(void);
+int nx_disp_top_close_module(void);
+int nx_disp_top_check_busy(void);
+
+enum mux_index {
+	primary_mlc = 0,
+	secondary_mlc = 1,
+	resolution_conv = 2,
+};
+
+enum prim_pad_mux_index {
+	padmux_primary_mlc = 0,
+	padmux_primary_mpu = 1,
+	padmux_secondary_mlc = 2,
+	padmux_resolution_conv = 3,
+};
+
+void nx_disp_top_set_resconvmux(int benb, u32 sel);
+void nx_disp_top_set_hdmimux(int benb, u32 sel);
+void nx_disp_top_set_mipimux(int benb, u32 sel);
+void nx_disp_top_set_lvdsmux(int benb, u32 sel);
+void nx_disp_top_set_primary_mux(u32 sel);
+void nx_disp_top_hdmi_set_vsync_start(u32 sel);
+void nx_disp_top_hdmi_set_vsync_hsstart_end(u32 start, u32 end);
+void nx_disp_top_hdmi_set_hactive_start(u32 sel);
+void nx_disp_top_hdmi_set_hactive_end(u32 sel);
+
+void nx_disp_top_set_hdmifield(u32 enable, u32 init_val, u32 vsynctoggle,
+			       u32 hsynctoggle, u32 vsyncclr, u32 hsyncclr,
+			       u32 field_use, u32 muxsel);
+
+enum padclk_config {
+	padclk_clk = 0,
+	padclk_inv_clk = 1,
+	padclk_reserved_clk = 2,
+	padclk_reserved_inv_clk = 3,
+	padclk_clk_div2_0 = 4,
+	padclk_clk_div2_90 = 5,
+	padclk_clk_div2_180 = 6,
+	padclk_clk_div2_270 = 7,
+};
+
+void nx_disp_top_set_padclock(u32 mux_index, u32 padclk_cfg);
+void nx_disp_top_set_lcdif_enb(int enb);
+void nx_disp_top_set_hdmifield(u32 enable, u32 init_val, u32 vsynctoggle,
+			       u32 hsynctoggle, u32 vsyncclr, u32 hsyncclr,
+			       u32 field_use, u32 muxsel);
+
+#endif
diff --git a/drivers/video/nexell/soc/s5pxx18_soc_disptop_clk.c b/drivers/video/nexell/soc/s5pxx18_soc_disptop_clk.c
new file mode 100644
index 0000000..02361ba
--- /dev/null
+++ b/drivers/video/nexell/soc/s5pxx18_soc_disptop_clk.c
@@ -0,0 +1,309 @@ 
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2016  Nexell Co., Ltd.
+ *
+ * Author: junghyun, kim <jhkim at nexell.co.kr>
+ */
+
+#include <linux/types.h>
+#include <linux/io.h>
+
+#include "s5pxx18_soc_disptop_clk.h"
+#include "s5pxx18_soc_disptop.h"
+
+static struct {
+	struct nx_disptop_clkgen_register_set *__g_pregister;
+} __g_module_variables[NUMBER_OF_DISPTOP_CLKGEN_MODULE] = {
+	{ NULL,},
+};
+
+int nx_disp_top_clkgen_initialize(void)
+{
+	static int binit;
+	u32 i;
+
+	if (binit == 0) {
+		for (i = 0; i < NUMBER_OF_DISPTOP_CLKGEN_MODULE; i++)
+			__g_module_variables[i].__g_pregister = NULL;
+		binit = 1;
+	}
+	return 1;
+}
+
+u32 nx_disp_top_clkgen_get_number_of_module(void)
+{
+	return NUMBER_OF_DISPTOP_CLKGEN_MODULE;
+}
+
+u32 nx_disp_top_clkgen_get_physical_address(u32 module_index)
+{
+	static const u32 physical_addr[] =
+		PHY_BASEADDR_DISPTOP_CLKGEN_LIST;
+
+	return (u32)physical_addr[module_index];
+}
+
+u32 nx_disp_top_clkgen_get_size_of_register_set(void)
+{
+	return sizeof(struct nx_disptop_clkgen_register_set);
+}
+
+void nx_disp_top_clkgen_set_base_address(u32 module_index, void *base_address)
+{
+	__g_module_variables[module_index].__g_pregister =
+	    (struct nx_disptop_clkgen_register_set *)base_address;
+}
+
+void *nx_disp_top_clkgen_get_base_address(u32 module_index)
+{
+	return (void *)__g_module_variables[module_index].__g_pregister;
+}
+
+void nx_disp_top_clkgen_set_clock_bclk_mode(u32 module_index,
+					    enum nx_bclkmode mode)
+{
+	register struct nx_disptop_clkgen_register_set *pregister;
+	register u32 regvalue;
+	u32 clkmode = 0;
+
+	pregister = __g_module_variables[module_index].__g_pregister;
+	switch (mode) {
+	case nx_bclkmode_disable:
+		clkmode = 0;
+	case nx_bclkmode_dynamic:
+		clkmode = 2;
+		break;
+	case nx_bclkmode_always:
+		clkmode = 3;
+		break;
+	default:
+		break;
+	}
+
+	regvalue = pregister->clkenb;
+	regvalue &= ~3ul;
+	regvalue |= (clkmode & 0x03);
+
+	writel(regvalue, &pregister->clkenb);
+}
+
+enum nx_bclkmode nx_disp_top_clkgen_get_clock_bclk_mode(u32 module_index)
+{
+	register struct nx_disptop_clkgen_register_set *pregister;
+	u32 mode = 0;
+
+	pregister = __g_module_variables[module_index].__g_pregister;
+	mode = (pregister->clkenb & 3ul);
+
+	switch (mode) {
+	case 0:
+		return nx_bclkmode_disable;
+	case 2:
+		return nx_bclkmode_dynamic;
+	case 3:
+		return nx_bclkmode_always;
+	default:
+		break;
+	}
+	return nx_bclkmode_disable;
+}
+
+void nx_disp_top_clkgen_set_clock_pclk_mode(u32 module_index,
+					    enum nx_pclkmode mode)
+{
+	register struct nx_disptop_clkgen_register_set *pregister;
+	register u32 regvalue;
+	const u32 pclkmode_pos = 3;
+	u32 clkmode = 0;
+
+	pregister = __g_module_variables[module_index].__g_pregister;
+	switch (mode) {
+	case nx_pclkmode_dynamic:
+		clkmode = 0;
+		break;
+	case nx_pclkmode_always:
+		clkmode = 1;
+		break;
+	default:
+		break;
+	}
+
+	regvalue = pregister->clkenb;
+	regvalue &= ~(1ul << pclkmode_pos);
+	regvalue |= (clkmode & 0x01) << pclkmode_pos;
+
+	writel(regvalue, &pregister->clkenb);
+}
+
+enum nx_pclkmode nx_disp_top_clkgen_get_clock_pclk_mode(u32 module_index)
+{
+	register struct nx_disptop_clkgen_register_set *pregister;
+	const u32 pclkmode_pos = 3;
+
+	pregister = __g_module_variables[module_index].__g_pregister;
+
+	if (pregister->clkenb & (1ul << pclkmode_pos))
+		return nx_pclkmode_always;
+
+	return nx_pclkmode_dynamic;
+}
+
+void nx_disp_top_clkgen_set_clock_source(u32 module_index, u32 index,
+					 u32 clk_src)
+{
+	register struct nx_disptop_clkgen_register_set *pregister;
+	register u32 read_value;
+
+	const u32 clksrcsel_pos = 2;
+	const u32 clksrcsel_mask = 0x07 << clksrcsel_pos;
+
+	pregister = __g_module_variables[module_index].__g_pregister;
+
+	read_value = pregister->CLKGEN[index << 1];
+	read_value &= ~clksrcsel_mask;
+	read_value |= clk_src << clksrcsel_pos;
+
+	writel(read_value, &pregister->CLKGEN[index << 1]);
+}
+
+u32 nx_disp_top_clkgen_get_clock_source(u32 module_index, u32 index)
+{
+	register struct nx_disptop_clkgen_register_set *pregister;
+	const u32 clksrcsel_pos = 2;
+	const u32 clksrcsel_mask = 0x07 << clksrcsel_pos;
+
+	pregister = __g_module_variables[module_index].__g_pregister;
+
+	return (pregister->CLKGEN[index << 1] &
+		clksrcsel_mask) >> clksrcsel_pos;
+}
+
+void nx_disp_top_clkgen_set_clock_divisor(u32 module_index, u32 index,
+					  u32 divisor)
+{
+	register struct nx_disptop_clkgen_register_set *pregister;
+	const u32 clkdiv_pos = 5;
+	const u32 clkdiv_mask = 0xff << clkdiv_pos;
+	register u32 read_value;
+
+	pregister = __g_module_variables[module_index].__g_pregister;
+
+	read_value = pregister->CLKGEN[index << 1];
+	read_value &= ~clkdiv_mask;
+	read_value |= (divisor - 1) << clkdiv_pos;
+	writel(read_value, &pregister->CLKGEN[index << 1]);
+}
+
+u32 nx_disp_top_clkgen_get_clock_divisor(u32 module_index, u32 index)
+{
+	register struct nx_disptop_clkgen_register_set *pregister;
+	const u32 clkdiv_pos = 5;
+	const u32 clkdiv_mask = 0xff << clkdiv_pos;
+
+	pregister = __g_module_variables[module_index].__g_pregister;
+
+	return ((pregister->CLKGEN[index << 1] &
+		 clkdiv_mask) >> clkdiv_pos) + 1;
+}
+
+void nx_disp_top_clkgen_set_clock_divisor_enable(u32 module_index, int enable)
+{
+	register struct nx_disptop_clkgen_register_set *pregister;
+	register u32 read_value;
+	const u32 clkgenenb_pos = 2;
+	const u32 clkgenenb_mask = 1ul << clkgenenb_pos;
+
+	pregister = __g_module_variables[module_index].__g_pregister;
+
+	read_value = pregister->clkenb;
+	read_value &= ~clkgenenb_mask;
+	read_value |= (u32)enable << clkgenenb_pos;
+
+	writel(read_value, &pregister->clkenb);
+}
+
+int nx_disp_top_clkgen_get_clock_divisor_enable(u32 module_index)
+{
+	register struct nx_disptop_clkgen_register_set *pregister;
+	const u32 clkgenenb_pos = 2;
+	const u32 clkgenenb_mask = 1ul << clkgenenb_pos;
+
+	pregister = __g_module_variables[module_index].__g_pregister;
+
+	return (int)((pregister->clkenb &
+		      clkgenenb_mask) >> clkgenenb_pos);
+}
+
+void nx_disp_top_clkgen_set_clock_out_inv(u32 module_index, u32 index,
+					  int out_clk_inv)
+{
+	register struct nx_disptop_clkgen_register_set *pregister;
+	register u32 read_value;
+	const u32 outclkinv_pos = 1;
+	const u32 outclkinv_mask = 1ul << outclkinv_pos;
+
+	pregister = __g_module_variables[module_index].__g_pregister;
+
+	read_value = pregister->CLKGEN[index << 1];
+	read_value &= ~outclkinv_mask;
+	read_value |= out_clk_inv << outclkinv_pos;
+
+	writel(read_value, &pregister->CLKGEN[index << 1]);
+}
+
+int nx_disp_top_clkgen_get_clock_out_inv(u32 module_index, u32 index)
+{
+	register struct nx_disptop_clkgen_register_set *pregister;
+	const u32 outclkinv_pos = 1;
+	const u32 outclkinv_mask = 1ul << outclkinv_pos;
+
+	pregister = __g_module_variables[module_index].__g_pregister;
+
+	return (int)((pregister->CLKGEN[index << 1] &
+		      outclkinv_mask) >> outclkinv_pos);
+}
+
+int nx_disp_top_clkgen_set_input_inv(u32 module_index,
+				     u32 index, int in_clk_inv)
+{
+	register struct nx_disptop_clkgen_register_set *pregister;
+	register u32 read_value;
+	const u32 inclkinv_pos = 4 + index;
+	const u32 inclkinv_mask = 1ul << inclkinv_pos;
+
+	pregister = __g_module_variables[module_index].__g_pregister;
+
+	read_value = pregister->clkenb;
+	read_value &= ~inclkinv_mask;
+	read_value |= in_clk_inv << inclkinv_pos;
+
+	writel(read_value, &pregister->clkenb);
+	return true;
+}
+
+int nx_disp_top_clkgen_get_input_inv(u32 module_index, u32 index)
+{
+	register struct nx_disptop_clkgen_register_set *pregister;
+	const u32 inclkinv_pos = 4 + index;
+	const u32 inclkinv_mask = 1ul << inclkinv_pos;
+
+	pregister = __g_module_variables[module_index].__g_pregister;
+
+	return (int)((pregister->clkenb &
+		      inclkinv_mask) >> inclkinv_pos);
+}
+
+void nx_disp_top_clkgen_set_clock_out_select(u32 module_index, u32 index,
+					     int bbypass)
+{
+	register struct nx_disptop_clkgen_register_set *pregister;
+	register u32 read_value;
+
+	pregister = __g_module_variables[module_index].__g_pregister;
+
+	read_value = pregister->CLKGEN[index << 1];
+	read_value = read_value & (~0x01);
+	read_value = read_value | bbypass;
+
+	writel(read_value, &pregister->CLKGEN[index << 1]);
+}
diff --git a/drivers/video/nexell/soc/s5pxx18_soc_disptop_clk.h b/drivers/video/nexell/soc/s5pxx18_soc_disptop_clk.h
new file mode 100644
index 0000000..d55fef7
--- /dev/null
+++ b/drivers/video/nexell/soc/s5pxx18_soc_disptop_clk.h
@@ -0,0 +1,59 @@ 
+/* SPDX-License-Identifier: GPL-2.0+
+ *
+ * Copyright (C) 2016  Nexell Co., Ltd.
+ *
+ * Author: junghyun, kim <jhkim at nexell.co.kr>
+ */
+
+#ifndef _S5PXX18_SOC_DISPTOP_CLK_H_
+#define _S5PXX18_SOC_DISPTOP_CLK_H_
+
+#include "s5pxx18_soc_disptype.h"
+
+#define	PHY_BASEADDR_DISPTOP_CLKGEN_LIST	\
+		{ PHY_BASEADDR_DISPTOP_CLKGEN0_MODULE, \
+		  PHY_BASEADDR_DISPTOP_CLKGEN1_MODULE, \
+		  PHY_BASEADDR_DISPTOP_CLKGEN2_MODULE, \
+		  PHY_BASEADDR_DISPTOP_CLKGEN3_MODULE, \
+		  PHY_BASEADDR_DISPTOP_CLKGEN4_MODULE, \
+		}
+
+struct nx_disptop_clkgen_register_set {
+	u32 clkenb;
+	u32 CLKGEN[4];
+};
+
+int nx_disp_top_clkgen_initialize(void);
+u32 nx_disp_top_clkgen_get_number_of_module(void);
+u32 nx_disp_top_clkgen_get_physical_address(u32 module_index);
+u32 nx_disp_top_clkgen_get_size_of_register_set(void);
+void nx_disp_top_clkgen_set_base_address(u32 module_index,
+					 void *base_address);
+void *nx_disp_top_clkgen_get_base_address(u32 module_index);
+void nx_disp_top_clkgen_set_clock_pclk_mode(u32 module_index,
+					    enum nx_pclkmode mode);
+enum nx_pclkmode nx_disp_top_clkgen_get_clock_pclk_mode(u32 module_index);
+void nx_disp_top_clkgen_set_clock_source(u32 module_index, u32 index,
+					 u32 clk_src);
+u32 nx_disp_top_clkgen_get_clock_source(u32 module_index, u32 index);
+void nx_disp_top_clkgen_set_clock_divisor(u32 module_index, u32 index,
+					  u32 divisor);
+u32 nx_disp_top_clkgen_get_clock_divisor(u32 module_index, u32 index);
+void nx_disp_top_clkgen_set_clock_divisor_enable(u32 module_index,
+						 int enable);
+int nx_disp_top_clkgen_get_clock_divisor_enable(u32 module_index);
+void nx_disp_top_clkgen_set_clock_bclk_mode(u32 module_index,
+					    enum nx_bclkmode mode);
+enum nx_bclkmode nx_disp_top_clkgen_get_clock_bclk_mode(u32 module_index);
+
+void nx_disp_top_clkgen_set_clock_out_inv(u32 module_index, u32 index,
+					  int out_clk_inv);
+int nx_disp_top_clkgen_get_clock_out_inv(u32 module_index, u32 index);
+int nx_disp_top_clkgen_set_input_inv(u32 module_index, u32 index,
+				     int out_clk_inv);
+int nx_disp_top_clkgen_get_input_inv(u32 module_index, u32 index);
+
+void nx_disp_top_clkgen_set_clock_out_select(u32 module_index, u32 index,
+					     int bbypass);
+
+#endif
diff --git a/drivers/video/nexell/soc/s5pxx18_soc_disptype.h b/drivers/video/nexell/soc/s5pxx18_soc_disptype.h
new file mode 100644
index 0000000..b5df7a7
--- /dev/null
+++ b/drivers/video/nexell/soc/s5pxx18_soc_disptype.h
@@ -0,0 +1,23 @@ 
+/* SPDX-License-Identifier: GPL-2.0+
+ *
+ * Copyright (C) 2016  Nexell Co., Ltd.
+ *
+ * Author: junghyun, kim <jhkim at nexell.co.kr>
+ */
+
+#ifndef _S5PXX18_SOC_DISP_TYPE_H_
+#define _S5PXX18_SOC_DISP_TYPE_H_
+
+/* clock control types */
+enum nx_pclkmode {
+	nx_pclkmode_dynamic = 0UL,
+	nx_pclkmode_always	= 1UL
+};
+
+enum nx_bclkmode {
+	nx_bclkmode_disable	= 0UL,
+	nx_bclkmode_dynamic	= 2UL,
+	nx_bclkmode_always	= 3UL
+};
+
+#endif