diff mbox series

arm64: versal: Disable DDR cache mapping if DDR is not enabled

Message ID d40c43fce69bc66ffc5cbcd69c45c7021905eab2.1584974673.git.michal.simek@xilinx.com
State Accepted
Commit 98da86681e5158195314fd5df4ff605d3bb63d75
Headers show
Series arm64: versal: Disable DDR cache mapping if DDR is not enabled | expand

Commit Message

Michal Simek March 23, 2020, 2:44 p.m. UTC 
Similar change was done in past by commit 3b644a3c2f69
("arm64: zynqmp: Provide a config to not map DDR region in MMU table").

Signed-off-by: Michal Simek <michal.simek at xilinx.com>
---

 arch/arm/mach-versal/Kconfig | 6 ++++++
 arch/arm/mach-versal/cpu.c   | 9 +++++++++
 2 files changed, 15 insertions(+)
diff mbox series

Patch

diff --git a/arch/arm/mach-versal/Kconfig b/arch/arm/mach-versal/Kconfig
index a08e5ae41490..e1d66e8d32b7 100644
--- a/arch/arm/mach-versal/Kconfig
+++ b/arch/arm/mach-versal/Kconfig
@@ -56,4 +56,10 @@  config DEFINE_TCM_OCM_MMAP
 	  This option if enabled defines the TCM and OCM memory and its
 	  memory attributes in MMU table entry.
 
+config VERSAL_NO_DDR
+	bool "Disable DDR MMU mapping"
+	help
+	  This option configures MMU with no DDR to avoid speculative
+	  access to DDR memory where DDR is not present.
+
 endif
diff --git a/arch/arm/mach-versal/cpu.c b/arch/arm/mach-versal/cpu.c
index 6ee6cd43eca4..829a6c1b3e53 100644
--- a/arch/arm/mach-versal/cpu.c
+++ b/arch/arm/mach-versal/cpu.c
@@ -81,6 +81,15 @@  void mem_map_fill(void)
 		if (!gd->bd->bi_dram[i].size)
 			break;
 
+#if defined(CONFIG_VERSAL_NO_DDR)
+		if (gd->bd->bi_dram[i].start < 0x80000000UL ||
+		    gd->bd->bi_dram[i].start > 0x100000000UL) {
+			printf("Ignore caches over %llx/%llx\n",
+			       gd->bd->bi_dram[i].start,
+			       gd->bd->bi_dram[i].size);
+			continue;
+		}
+#endif
 		versal_mem_map[banks].virt = gd->bd->bi_dram[i].start;
 		versal_mem_map[banks].phys = gd->bd->bi_dram[i].start;
 		versal_mem_map[banks].size = gd->bd->bi_dram[i].size;