@@ -940,6 +940,21 @@
clocks = <&clk_sandbox 4>;
power-domains = <&pwrdom 1>;
};
+
+ resetc2: syscon-reset {
+ compatible = "syscon-reset";
+ #reset-cells = <1>;
+ regmap = <&syscon0>;
+ offset = <1>;
+ mask = <0x27FFFFFF>;
+ assert-high = <0>;
+ };
+
+ syscon-reset-test {
+ compatible = "sandbox,misc_sandbox";
+ resets = <&resetc2 15>, <&resetc2 30>, <&resetc2 60>;
+ reset-names = "valid", "no_mask", "out_of_range";
+ };
};
#include "sandbox_pmic.dtsi"
@@ -190,6 +190,8 @@ CONFIG_REMOTEPROC_SANDBOX=y
CONFIG_DM_RESET=y
CONFIG_SANDBOX_RESET=y
CONFIG_DM_RNG=y
+CONFIG_RNG_SANDBOX=y
+CONFIG_RESET_SYSCON=y
CONFIG_DM_RTC=y
CONFIG_RTC_RV8803=y
CONFIG_DEBUG_UART_SANDBOX=y
new file mode 100644
@@ -0,0 +1,36 @@
+Generic SYSCON mapped register reset driver
+
+This is a generic reset driver using syscon to map the reset register.
+The reset is generally performed with a write to the reset register
+defined by the register map pointed by syscon reference plus the offset and
+shifted by the reset specifier/
+
+To assert a reset on some device, the equivalent of the following operation is
+performed, where reset_id is the reset specifier from the device's resets
+property.
+
+ if (BIT(reset_id) & mask)
+ regmap[offset][reset_id] = assert-high;
+
+Required properties:
+- compatible: should contain "syscon-reset"
+- #reset-cells: must be 1
+- regmap: this is phandle to the register map node
+- offset: offset in the register map for the reboot register (in bytes)
+
+Optional properties:
+- mask: accept only the reset specifiers defined by the mask (32 bit)
+- assert-high: Bit to write when asserting a reset. Defaults to 1.
+
+Default will be little endian mode, 32 bit access only.
+
+Example:
+
+ reset-controller {
+ compatible = "syscon-reset";
+ #reset-cells = <1>;
+ regmap = <&sysctl>;
+ offset = <0x20>;
+ mask = <0x27FFFFFF>;
+ assert-high = <0>;
+ };
@@ -148,4 +148,9 @@ config RESET_IMX7
help
Support for reset controller on i.MX7/8 SoCs.
+config RESET_SYSCON
+ bool "Enable generic syscon reset driver support"
+ depends on DM_RESET
+ help
+ Support generic syscon mapped register reset devices.
endmenu
@@ -23,3 +23,4 @@ obj-$(CONFIG_RESET_MTMIPS) += reset-mtmips.o
obj-$(CONFIG_RESET_SUNXI) += reset-sunxi.o
obj-$(CONFIG_RESET_HISILICON) += reset-hisilicon.o
obj-$(CONFIG_RESET_IMX7) += reset-imx7.o
+obj-$(CONFIG_RESET_SYSCON) += reset-syscon.o
new file mode 100644
@@ -0,0 +1,80 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2020 Sean Anderson
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <regmap.h>
+#include <reset.h>
+#include <reset-uclass.h>
+#include <syscon.h>
+#include <linux/err.h>
+
+struct syscon_reset_priv {
+ struct regmap *regmap;
+ uint offset;
+ uint mask;
+ bool assert_high;
+};
+
+static int syscon_reset_request(struct reset_ctl *rst)
+{
+ struct syscon_reset_priv *priv = dev_get_priv(rst->dev);
+
+ if (BIT(rst->id) & priv->mask)
+ return 0;
+ else
+ return -EINVAL;
+}
+
+static int syscon_reset_assert(struct reset_ctl *rst)
+{
+ struct syscon_reset_priv *priv = dev_get_priv(rst->dev);
+
+ return regmap_update_bits(priv->regmap, priv->offset, BIT(rst->id),
+ priv->assert_high ? BIT(rst->id) : 0);
+}
+
+static int syscon_reset_deassert(struct reset_ctl *rst)
+{
+ struct syscon_reset_priv *priv = dev_get_priv(rst->dev);
+
+ return regmap_update_bits(priv->regmap, priv->offset, BIT(rst->id),
+ priv->assert_high ? 0 : BIT(rst->id));
+}
+
+static const struct reset_ops syscon_reset_ops = {
+ .request = syscon_reset_request,
+ .rst_assert = syscon_reset_assert,
+ .rst_deassert = syscon_reset_deassert,
+};
+
+int syscon_reset_probe(struct udevice *dev)
+{
+ struct syscon_reset_priv *priv = dev_get_priv(dev);
+
+ priv->regmap = syscon_regmap_lookup_by_phandle(dev, "regmap");
+ if (IS_ERR(priv->regmap))
+ return -ENODEV;
+
+ priv->offset = dev_read_u32_default(dev, "offset", 0);
+ priv->mask = dev_read_u32_default(dev, "mask", 0);
+ priv->assert_high = dev_read_u32_default(dev, "assert-high", true);
+
+ return 0;
+}
+
+static const struct udevice_id syscon_reset_ids[] = {
+ { .compatible = "syscon-reset" },
+ { },
+};
+
+U_BOOT_DRIVER(syscon_reset) = {
+ .name = "syscon_reset",
+ .id = UCLASS_RESET,
+ .of_match = syscon_reset_ids,
+ .probe = syscon_reset_probe,
+ .priv_auto_alloc_size = sizeof(struct syscon_reset_priv),
+ .ops = &syscon_reset_ops,
+};
@@ -72,4 +72,5 @@ obj-$(CONFIG_DM_MDIO_MUX) += mdio_mux.o
obj-$(CONFIG_DM_RNG) += rng.o
obj-$(CONFIG_CLK_K210_SET_RATE) += k210_pll.o
obj-$(CONFIG_SIMPLE_PM_BUS) += simple-pm-bus.o
+obj-$(CONFIG_RESET_SYSCON) += syscon-reset.o
endif
new file mode 100644
@@ -0,0 +1,58 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2020 Sean Anderson <seanga2 at gmail.com>
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <dm/test.h>
+#include <regmap.h>
+#include <reset.h>
+#include <syscon.h>
+#include <test/ut.h>
+#include <asm/test.h>
+
+/* The following values must match the device tree */
+#define TEST_RESET_REG 1
+#define TEST_RESET_ASSERT_HIGH 0
+#define TEST_RESET_ASSERT (TEST_RESET_ASSERT_HIGH ? (u32)-1 : (u32)0)
+#define TEST_RESET_DEASSERT (~TEST_RESET_ASSERT)
+
+#define TEST_RESET_VALID 15
+#define TEST_RESET_NOMASK 30
+#define TEST_RESET_OUTOFRANGE 60
+
+static int dm_test_syscon_reset(struct unit_test_state *uts)
+{
+ struct regmap *map;
+ struct reset_ctl rst;
+ struct udevice *reset;
+ struct udevice *syscon;
+ struct udevice *syscon_reset;
+ uint reg;
+
+ ut_assertok(uclass_get_device_by_name(UCLASS_MISC, "syscon-reset-test",
+ &reset));
+ ut_assertok(uclass_get_device_by_name(UCLASS_SYSCON, "syscon at 0",
+ &syscon));
+ ut_assertok(uclass_get_device_by_name(UCLASS_RESET, "syscon-reset",
+ &syscon_reset));
+ ut_assertok_ptr((map = syscon_get_regmap(syscon)));
+
+ ut_asserteq(-EINVAL, reset_get_by_name(reset, "no_mask", &rst));
+ ut_asserteq(-EINVAL, reset_get_by_name(reset, "out_of_range", &rst));
+ ut_assertok(reset_get_by_name(reset, "valid", &rst));
+
+ sandbox_set_enable_memio(true);
+ ut_assertok(regmap_write(map, TEST_RESET_REG, TEST_RESET_DEASSERT));
+ ut_assertok(reset_assert(&rst));
+ ut_assertok(regmap_read(map, TEST_RESET_REG, ®));
+ ut_asserteq(TEST_RESET_DEASSERT ^ BIT(TEST_RESET_VALID), reg);
+
+ ut_assertok(reset_deassert(&rst));
+ ut_assertok(regmap_read(map, TEST_RESET_REG, ®));
+ ut_asserteq(TEST_RESET_DEASSERT, reg);
+
+ return 0;
+}
+DM_TEST(dm_test_syscon_reset, DM_TESTF_SCAN_FDT);