diff mbox series

[v5,12/17] arm: socfpga: Add ATF support for Reset Manager driver

Message ID 1584019434-45856-13-git-send-email-chee.hong.ang@intel.com
State New
Headers show
Series Enable ARM Trusted Firmware for U-Boot | expand

Commit Message

Ang, Chee Hong March 12, 2020, 1:23 p.m. UTC 
From: Chee Hong Ang <chee.hong.ang at intel.com>

In non-secure mode (EL2), Reset Manager driver calls the
SMC/PSCI services provided by ATF to enable/disable the
SOCFPGA bridges.

Signed-off-by: Chee Hong Ang <chee.hong.ang at intel.com>
---
 arch/arm/mach-socfpga/reset_manager_s10.c | 10 ++++++++++
 1 file changed, 10 insertions(+)
diff mbox series

Patch

diff --git a/arch/arm/mach-socfpga/reset_manager_s10.c b/arch/arm/mach-socfpga/reset_manager_s10.c
index c743077..c028e2d 100644
--- a/arch/arm/mach-socfpga/reset_manager_s10.c
+++ b/arch/arm/mach-socfpga/reset_manager_s10.c
@@ -5,10 +5,13 @@ 
  */
 
 #include <common.h>
+#include <hang.h>
 #include <asm/io.h>
+#include <asm/arch/misc.h>
 #include <asm/arch/reset_manager.h>
 #include <asm/arch/system_manager.h>
 #include <dt-bindings/reset/altr,rst-mgr-s10.h>
+#include <linux/intel-smc.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -54,6 +57,12 @@  void socfpga_per_reset_all(void)
 
 void socfpga_bridges_reset(int enable)
 {
+#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_ATF)
+	u64 arg = enable;
+
+	if (invoke_smc(INTEL_SIP_SMC_HPS_SET_BRIDGES, &arg, 1, NULL, 0))
+		hang();
+#else
 	if (enable) {
 		/* clear idle request to all bridges */
 		setbits_le32(socfpga_get_sysmgr_addr() +
@@ -94,6 +103,7 @@  void socfpga_bridges_reset(int enable)
 		/* Disable NOC timeout */
 		writel(0, socfpga_get_sysmgr_addr() + SYSMGR_SOC64_NOC_TIMEOUT);
 	}
+#endif
 }
 
 /*