@@ -6,6 +6,7 @@
#include "skeleton.dtsi"
#include "dt-bindings/clock/snps,hsdk-cgu.h"
+#include "dt-bindings/reset/snps,hsdk-reset.h"
/ {
model = "snps,hsdk";
@@ -62,6 +63,12 @@
#clock-cells = <1>;
};
+ cgu_rst: reset-controller at f00008a0 {
+ compatible = "snps,hsdk-reset";
+ #reset-cells = <1>;
+ reg = <0xf00008a0 0x4>, <0xf0000ff0 0x4>;
+ };
+
uart0: serial0 at f0005000 {
compatible = "snps,dw-apb-uart";
reg = <0xf0005000 0x1000>;
@@ -47,6 +47,7 @@ CONFIG_SPI_FLASH_SST=y
CONFIG_DM_ETH=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_MII=y
+CONFIG_DM_RESET=y
CONFIG_DM_SERIAL=y
CONFIG_DEBUG_UART_SHIFT=2
CONFIG_DEBUG_UART_ANNOUNCE=y
As the driver of on-chip reset controller became available we are ready to enable it. Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev at synopsys.com> --- arch/arc/dts/hsdk.dts | 7 +++++++ configs/hsdk_defconfig | 1 + 2 files changed, 8 insertions(+)