| Message ID | 20200306111355.5.I2f3d97c071fc1de6dae7e15ee0bbc1df0f16fd9a@changeid |
|---|---|
| State | Accepted |
| Commit | 27e7b4edeabe87be1cb9dc549b2f7d91c1f3e3a7 |
| Headers | show |
| Series | ram: stm32mp1: fixes | expand |
On 3/6/20 11:14 AM, Patrick Delaunay wrote: > The derating (timing parameter derating using MR4 read value) > can't be activated during BIST test, as the MR4 read answer will > be not understood by BIST (BISTGSR.BDONE bit stay at 0, > BISTWCSR.DXWCNT = 0x206 instead of BISTWCR.BWCNT = 0x200). > > This patch only impacts the tuning on LPDDR2/LPDDR3, > if derateen.derate_enable = 1. > > Signed-off-by: Patrick Delaunay <patrick.delaunay at st.com> > --- > > drivers/ram/stm32mp1/stm32mp1_tuning.c | 15 +++++++++++++++ > 1 file changed, 15 insertions(+) > > diff --git a/drivers/ram/stm32mp1/stm32mp1_tuning.c b/drivers/ram/stm32mp1/stm32mp1_tuning.c > index cab6cf087a..37d3ec8fef 100644 > --- a/drivers/ram/stm32mp1/stm32mp1_tuning.c > +++ b/drivers/ram/stm32mp1/stm32mp1_tuning.c > @@ -1288,11 +1288,16 @@ static enum test_result do_read_dqs_gating(struct stm32mp1_ddrctl *ctl, > { > u32 rfshctl3 = readl(&ctl->rfshctl3); > u32 pwrctl = readl(&ctl->pwrctl); > + u32 derateen = readl(&ctl->derateen); > enum test_result res; > > + writel(0x0, &ctl->derateen); > stm32mp1_refresh_disable(ctl); > + > res = read_dqs_gating(ctl, phy, string); > + > stm32mp1_refresh_restore(ctl, rfshctl3, pwrctl); > + writel(derateen, &ctl->derateen); > > return res; > } > @@ -1303,11 +1308,16 @@ static enum test_result do_bit_deskew(struct stm32mp1_ddrctl *ctl, > { > u32 rfshctl3 = readl(&ctl->rfshctl3); > u32 pwrctl = readl(&ctl->pwrctl); > + u32 derateen = readl(&ctl->derateen); > enum test_result res; > > + writel(0x0, &ctl->derateen); > stm32mp1_refresh_disable(ctl); > + > res = bit_deskew(ctl, phy, string); > + > stm32mp1_refresh_restore(ctl, rfshctl3, pwrctl); > + writel(derateen, &ctl->derateen); > > return res; > } > @@ -1318,11 +1328,16 @@ static enum test_result do_eye_training(struct stm32mp1_ddrctl *ctl, > { > u32 rfshctl3 = readl(&ctl->rfshctl3); > u32 pwrctl = readl(&ctl->pwrctl); > + u32 derateen = readl(&ctl->derateen); > enum test_result res; > > + writel(0x0, &ctl->derateen); > stm32mp1_refresh_disable(ctl); > + > res = eye_training(ctl, phy, string); > + > stm32mp1_refresh_restore(ctl, rfshctl3, pwrctl); > + writel(derateen, &ctl->derateen); > > return res; > } Acked-by: Patrice Chotard <patrice.chotard at st.com> Thanks Patrice
Hi, > From: Patrick DELAUNAY <patrick.delaunay at st.com> > Sent: vendredi 6 mars 2020 11:14 > > The derating (timing parameter derating using MR4 read value) can't be activated > during BIST test, as the MR4 read answer will be not understood by BIST > (BISTGSR.BDONE bit stay at 0, BISTWCSR.DXWCNT = 0x206 instead of > BISTWCR.BWCNT = 0x200). > > This patch only impacts the tuning on LPDDR2/LPDDR3, if > derateen.derate_enable = 1. > > Signed-off-by: Patrick Delaunay <patrick.delaunay at st.com> > --- Applied to u-boot-stm/next, thanks! Regards Patrick
diff --git a/drivers/ram/stm32mp1/stm32mp1_tuning.c b/drivers/ram/stm32mp1/stm32mp1_tuning.c index cab6cf087a..37d3ec8fef 100644 --- a/drivers/ram/stm32mp1/stm32mp1_tuning.c +++ b/drivers/ram/stm32mp1/stm32mp1_tuning.c @@ -1288,11 +1288,16 @@ static enum test_result do_read_dqs_gating(struct stm32mp1_ddrctl *ctl, { u32 rfshctl3 = readl(&ctl->rfshctl3); u32 pwrctl = readl(&ctl->pwrctl); + u32 derateen = readl(&ctl->derateen); enum test_result res; + writel(0x0, &ctl->derateen); stm32mp1_refresh_disable(ctl); + res = read_dqs_gating(ctl, phy, string); + stm32mp1_refresh_restore(ctl, rfshctl3, pwrctl); + writel(derateen, &ctl->derateen); return res; } @@ -1303,11 +1308,16 @@ static enum test_result do_bit_deskew(struct stm32mp1_ddrctl *ctl, { u32 rfshctl3 = readl(&ctl->rfshctl3); u32 pwrctl = readl(&ctl->pwrctl); + u32 derateen = readl(&ctl->derateen); enum test_result res; + writel(0x0, &ctl->derateen); stm32mp1_refresh_disable(ctl); + res = bit_deskew(ctl, phy, string); + stm32mp1_refresh_restore(ctl, rfshctl3, pwrctl); + writel(derateen, &ctl->derateen); return res; } @@ -1318,11 +1328,16 @@ static enum test_result do_eye_training(struct stm32mp1_ddrctl *ctl, { u32 rfshctl3 = readl(&ctl->rfshctl3); u32 pwrctl = readl(&ctl->pwrctl); + u32 derateen = readl(&ctl->derateen); enum test_result res; + writel(0x0, &ctl->derateen); stm32mp1_refresh_disable(ctl); + res = eye_training(ctl, phy, string); + stm32mp1_refresh_restore(ctl, rfshctl3, pwrctl); + writel(derateen, &ctl->derateen); return res; }
The derating (timing parameter derating using MR4 read value) can't be activated during BIST test, as the MR4 read answer will be not understood by BIST (BISTGSR.BDONE bit stay at 0, BISTWCSR.DXWCNT = 0x206 instead of BISTWCR.BWCNT = 0x200). This patch only impacts the tuning on LPDDR2/LPDDR3, if derateen.derate_enable = 1. Signed-off-by: Patrick Delaunay <patrick.delaunay at st.com> --- drivers/ram/stm32mp1/stm32mp1_tuning.c | 15 +++++++++++++++ 1 file changed, 15 insertions(+)