| Message ID | 20200305181308.944595-20-seanga2@gmail.com |
|---|---|
| State | New |
| Headers | show |
| Series | riscv: Add Sipeed Maix support | expand |
Hi Sean > The Sipeed Maix series is a collection of boards built around the RISC-V > Kendryte K210 processor. This processor contains several peripherals to > accelerate neural network processing and other "ai" tasks. This includes a > "KPU" neural network processor, an audio processor supporting beamforming > reception, and a digital video port supporting capture and output at VGA > resolution. Other peripherals include 8M of sram (accessible with and > without caching); remappable pins, including 40 GPIOs; AES, FFT, and SHA256 > accelerators; a DMA controller; and I2C, I2S, and SPI controllers. Maix > peripherals vary, but include spi flash; on-board usb-serial bridges; ports > for cameras, displays, and sd cards; and ESP32 chips. Currently, only the > Sipeed Maix Bit V2.0 (bitm) is supported, but the boards are fairly > similar. > > Documentation for Maix boards is located at > <http://dl.sipeed.com/MAIX/HDK/>. Documentation for the Kendryte K210 is > located at <https://kendryte.com/downloads/>. However, hardware details are > rather lacking, so most technical reference has been taken from the > standalone sdk located at > <https://github.com/kendryte/kendryte-standalone-sdk>. > > Signed-off-by: Sean Anderson <seanga2 at gmail.com> > --- This patch applying fail Applying: riscv: Add Sipeed Maix support error: patch failed: doc/board/index.rst:16 error: doc/board/index.rst: patch does not apply Patch failed at 0001 riscv: Add Sipeed Maix support The copy of the patch that failed is found in: .git/rebase-apply/patch When you have resolved this problem, run "git am --continue". If you prefer to skip this patch, run "git am --skip" instead. To restore the original branch and stop patching, run "git am --abort". I have replied to you the same result in v5 [v5,33/33] riscv: Add Sipeed Maix support https://patchwork.ozlabs.org/patch/1246869/#2376311 By the way, you can not mix them (arch, board, configs, doc)together in a patch. arch/riscv/Kconfig board/sipeed/maix/ ... configs/sipeed_maix_bitm_defconfig doc/board/index.rst Thanks, Rick > > Changes in v6: > - Remove trailing whitespace from documentation > - Remove configuration for spi/pinmux/gpio features > - Flesh out documentation some more > > Changes in v5: > - Configure relocation location with CONFIG_SYS_SDRAM_* > - Enable ram clocks > - Add pinmux/gpio/led support > - Remove (broken) MMC support > - Store the environment in flash > - Add partitions > - Add bootcmd > - Add docs for pinctrl and booting > > Changes in v4: > - Rework documentation to be organized by board mfg not cpu mfg > - Update docs to reflect working SPI support > - Add proper spi support > - Don't define unneecessary macros in config.h > - Lower the default stack so it isn't clobbered on relocation > - Update MAINTAINERS > - Update copyright > > Changes in v3: > - Reorder to be last in the patch series > - Add documentation for the board > - Generate defconfig with "make savedefconfig" > - Update Kconfig to imply most features we need > - Update MAINTAINERS > > Changes in v2: > - Select CONFIG_SYS_RISCV_NOCOUNTER > - Imply CONFIG_CLK_K210 > - Remove spurious references to CONFIG_ARCH_K210 > - Remove many configs from defconfig where the defaults were fine > - Add a few "not set" lines to suppress unneeded defaults > - Reduce pre-reloc malloc space, now that clocks initialization happens > later > > arch/riscv/Kconfig | 4 + > board/sipeed/maix/Kconfig | 48 +++++ > board/sipeed/maix/MAINTAINERS | 11 ++ > board/sipeed/maix/Makefile | 5 + > board/sipeed/maix/maix.c | 54 ++++++ > configs/sipeed_maix_bitm_defconfig | 8 + > doc/board/index.rst | 1 + > doc/board/sipeed/index.rst | 9 + > doc/board/sipeed/maix.rst | 298 +++++++++++++++++++++++++++++ > include/configs/sipeed-maix.h | 24 +++ > 10 files changed, 462 insertions(+) > create mode 100644 board/sipeed/maix/Kconfig > create mode 100644 board/sipeed/maix/MAINTAINERS > create mode 100644 board/sipeed/maix/Makefile > create mode 100644 board/sipeed/maix/maix.c > create mode 100644 configs/sipeed_maix_bitm_defconfig > create mode 100644 doc/board/sipeed/index.rst > create mode 100644 doc/board/sipeed/maix.rst > create mode 100644 include/configs/sipeed-maix.h > > diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig > index b7a5757584..d016dd75d7 100644 > --- a/arch/riscv/Kconfig > +++ b/arch/riscv/Kconfig > @@ -20,6 +20,9 @@ config TARGET_QEMU_VIRT > config TARGET_SIFIVE_FU540 > bool "Support SiFive FU540 Board" > > +config TARGET_SIPEED_MAIX > + bool "Support Sipeed Maix Board" > + > endchoice > > config SYS_ICACHE_OFF > @@ -53,6 +56,7 @@ source "board/AndesTech/ax25-ae350/Kconfig" > source "board/emulation/qemu-riscv/Kconfig" > source "board/microchip/mpfs_icicle/Kconfig" > source "board/sifive/fu540/Kconfig" > +source "board/sipeed/maix/Kconfig" > > # platform-specific options below > source "arch/riscv/cpu/ax25/Kconfig" > diff --git a/board/sipeed/maix/Kconfig b/board/sipeed/maix/Kconfig > new file mode 100644 > index 0000000000..8292089fc9 > --- /dev/null > +++ b/board/sipeed/maix/Kconfig > @@ -0,0 +1,48 @@ > +# SPDX-License-Identifier: GPL-2.0+ > +# Copyright (C) 2019-20 Sean Anderson <seanga2 at gmail.com> > + > +if TARGET_SIPEED_MAIX > + > +config SYS_BOARD > + default "maix" > + > +config SYS_VENDOR > + default "sipeed" > + > +config SYS_CPU > + default "generic" > + > +config SYS_CONFIG_NAME > + default "sipeed-maix" > + > +config SYS_TEXT_BASE > + default 0x80000000 > + > +config DEFAULT_DEVICE_TREE > + default "k210-maix-bit" > + > +config NR_CPUS > + default 2 > + > +config NR_DRAM_BANKS > + default 3 > + > +config BOARD_SPECIFIC_OPTIONS > + def_bool y > + select GENERIC_RISCV > + select RISCV_PRIV_1_9 > + imply SMP > + imply OF_BOARD_SETUP > + imply DM_SERIAL > + imply SIFIVE_SERIAL > + imply SIFIVE_CLINT > + imply POWER_DOMAIN > + imply SIMPLE_PM_BUS > + imply CLK_CCF > + imply CLK_COMPOSITE_CCF > + imply CLK_K210 > + imply DM_RESET > + imply RESET_SYSCON > + imply SYSRESET > + imply SYSRESET_SYSCON > +endif > diff --git a/board/sipeed/maix/MAINTAINERS b/board/sipeed/maix/MAINTAINERS > new file mode 100644 > index 0000000000..1f33882e1e > --- /dev/null > +++ b/board/sipeed/maix/MAINTAINERS > @@ -0,0 +1,11 @@ > +Sipeed Maix BOARD > +M: Sean Anderson <seanga2 at gmail.com> > +S: Maintained > +F: arch/riscv/dts/k210.dtsi > +F: arch/riscv/dts/k210-maix-bit.dts > +F: board/sipeed/maix/ > +F: configs/sipeed_maix_defconfig > +F: doc/board/sipeed/ > +F: include/configs/sipeed-maix.h > +F: include/dt-bindings/*/k210-sysctl.h > +F: test/dm/k210_pll.c > diff --git a/board/sipeed/maix/Makefile b/board/sipeed/maix/Makefile > new file mode 100644 > index 0000000000..4acff5b31e > --- /dev/null > +++ b/board/sipeed/maix/Makefile > @@ -0,0 +1,5 @@ > +# SPDX-License-Identifier: GPL-2.0+ > +# > +# Copyright (c) 2019 Western Digital Corporation or its affiliates. > + > +obj-y += maix.o > diff --git a/board/sipeed/maix/maix.c b/board/sipeed/maix/maix.c > new file mode 100644 > index 0000000000..c126cb5d67 > --- /dev/null > +++ b/board/sipeed/maix/maix.c > @@ -0,0 +1,54 @@ > +// SPDX-License-Identifier: GPL-2.0+ > +/* > + * Copyright (C) 2019 Sean Anderson <seanga2 at gmail.com> > + */ > + > +#include <common.h> > +#include <clk.h> > +#include <dm.h> > +#include <fdt_support.h> > + > +phys_size_t get_effective_memsize(void) > +{ > + return CONFIG_SYS_SDRAM_SIZE; > +} > + > +int board_init(void) > +{ > + int ret; > + ofnode bank = ofnode_null(); > + > + /* Enable RAM clocks */ > + while (true) { > + struct clk clk; > + > + bank = ofnode_by_prop_value(bank, "device_type", "memory", > + sizeof("memory")); > + if (ofnode_equal(bank, ofnode_null())) > + break; > + > + ret = clk_get_by_index_nodev(bank, 0, &clk); > + if (ret) > + continue; > + > + ret = clk_enable(&clk); > + clk_free(&clk); > + if (ret) > + return ret; > + } > + return 0; > +} > + > +int ft_board_setup(void *blob, bd_t *bd) > +{ > + int i; > + u64 base[CONFIG_NR_DRAM_BANKS]; > + u64 size[CONFIG_NR_DRAM_BANKS]; > + > + for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) { > + base[i] = bd->bi_dram[i].start; > + size[i] = bd->bi_dram[i].size; > + } > + > + return fdt_fixup_memory_banks(blob, base, size, CONFIG_NR_DRAM_BANKS); > +} > diff --git a/configs/sipeed_maix_bitm_defconfig b/configs/sipeed_maix_bitm_defconfig > new file mode 100644 > index 0000000000..f48f7f06e9 > --- /dev/null > +++ b/configs/sipeed_maix_bitm_defconfig > @@ -0,0 +1,8 @@ > +CONFIG_RISCV=y > +CONFIG_TARGET_SIPEED_MAIX=y > +CONFIG_ARCH_RV64I=y > +CONFIG_SYS_REDUNDAND_ENVIRONMENT=y > +# CONFIG_NET is not set > +# CONFIG_INPUT is not set > +# CONFIG_DM_ETH is not set > +# CONFIG_EFI_LOADER is not set > diff --git a/doc/board/index.rst b/doc/board/index.rst > index d43e536ca3..94f01bb098 100644 > --- a/doc/board/index.rst > +++ b/doc/board/index.rst > @@ -16,5 +16,6 @@ Board-specific doc > renesas/index > rockchip/index > sifive/index > + sipeed/index > st/index > xilinx/index > diff --git a/doc/board/sipeed/index.rst b/doc/board/sipeed/index.rst > new file mode 100644 > index 0000000000..3518e2d8f4 > --- /dev/null > +++ b/doc/board/sipeed/index.rst > @@ -0,0 +1,9 @@ > +.. SPDX-License-Identifier: GPL-2.0+ > + > +Sipeed > +====== > + > +.. toctree:: > + :maxdepth: 2 > + > + maix > diff --git a/doc/board/sipeed/maix.rst b/doc/board/sipeed/maix.rst > new file mode 100644 > index 0000000000..b11ee0182e > --- /dev/null > +++ b/doc/board/sipeed/maix.rst > @@ -0,0 +1,298 @@ > +.. SPDX-License-Identifier: GPL-2.0+ > +.. Copyright (C) 2020 Sean Anderson <seanga2 at gmail.com> > + > +Maix Bit > +======== > + > +Several of the Sipeed Maix series of boards cotain the Kendryte K210 processor, > +a 64-bit RISC-V CPU. This processor contains several peripherals to accelerate > +neural network processing and other "ai" tasks. This includes a "KPU" neural > +network processor, an audio processor supporting beamforming reception, and a > +digital video port supporting capture and output at VGA resolution. Other > +peripherals include 8M of SRAM (accessible with and without caching); remappable > +pins, including 40 GPIOs; AES, FFT, and SHA256 accelerators; a DMA controller; > +and I2C, I2S, and SPI controllers. Maix peripherals vary, but include spi flash; > +on-board usb-serial bridges; ports for cameras, displays, and sd cards; and > +ESP32 chips. Currently, only the Sipeed Maix Bit V2.0 (bitm) is supported, but > +the boards are fairly similar. > + > +Documentation for Maix boards is available from > +`Sipeed's website <http://dl.sipeed.com/MAIX/HDK/>`_. > +Documentation for the Kendryte K210 is available from > +`Kendryte's website <https://kendryte.com/downloads/>`_. However, hardware > +details are rather lacking, so most technical reference has been taken from the > +`standalone sdk <https://github.com/kendryte/kendryte-standalone-sdk>`_. > + > +Build and boot steps > +-------------------- > + > +To build u-boot, run > + > +.. code-block:: none > + > + make sipeed_maix_bitm_defconfig > + make CROSS_COMPILE=<your cross compile prefix> > + > +To flash u-boot to a maix bit, run > + > +.. code-block:: none > + > + kflash -tp /dev/<your tty here> -B bit_mic u-boot-dtb.bin > + > +Boot output should look like the following: > + > +.. code-block:: none > + > + U-Boot 2020.04-rc2-00087-g2221cc09c1-dirty (Feb 28 2020 - 13:53:09 -0500) > + > + DRAM: 8 MiB > + In: serial at 38000000 > + Out: serial at 38000000 > + Err: serial at 38000000 > + => > + > +Loading Images > +^^^^^^^^^^^^^^ > + > +To load a kernel, transfer it over serial. > + > +.. code-block:: none > + > + => loady 80000000 1500000 > + ## Switch baudrate to 1500000 bps and press ENTER ... > + > + *** baud: 1500000 > + > + *** baud: 1500000 *** > + ## Ready for binary (ymodem) download to 0x80000000 at 1500000 bps... > + C > + *** file: loader.bin > + $ sz -vv loader.bin > + Sending: loader.bin > + Bytes Sent:2478208 BPS:72937 > + Sending: > + Ymodem sectors/kbytes sent: 0/ 0k > + Transfer complete > + > + *** exit status: 0 *** > + ## Total Size = 0x0025d052 = 2478162 Bytes > + ## Switch baudrate to 115200 bps and press ESC ... > + > + *** baud: 115200 > + > + *** baud: 115200 *** > + => > + > +Running Programs > +^^^^^^^^^^^^^^^^ > + > +Binaries > +"""""""" > + > +To run a bare binary, use the ``go`` command: > + > +.. code-block:: none > + > + => loady > + ## Ready for binary (ymodem) download to 0x80000000 at 115200 bps... > + C > + *** file: ./examples/standalone/hello_world.bin > + $ sz -vv ./examples/standalone/hello_world.bin > + Sending: hello_world.bin > + Bytes Sent: 4864 BPS:649 > + Sending: > + Ymodem sectors/kbytes sent: 0/ 0k > + Transfer complete > + > + *** exit status: 0 *** > + (CAN) packets, 5 retries > + ## Total Size = 0x000012f8 = 4856 Bytes > + => go 80000000 > + ## Starting application at 0x80000000 ... > + Example expects ABI version 9 > + Actual U-Boot ABI version 9 > + Hello World > + argc = 1 > + argv[0] = "80000000" > + argv[1] = "<NULL>" > + Hit any key to exit ... > + > +Legacy Images > +""""""""""""" > + > +To run legacy images, use the ``bootm`` command: > + > +.. code-block:: none > + > + $ tools/mkimage -A riscv -O u-boot -T standalone -C none -a 80000000 -e 80000000 -d examples/standalone/hello_world.bin hello_world.img > + Image Name: > + Created: Thu Mar 5 12:04:10 2020 > + Image Type: RISC-V U-Boot Standalone Program (uncompressed) > + Data Size: 4856 Bytes = 4.74 KiB = 0.00 MiB > + Load Address: 80000000 > + Entry Point: 80000000 > + > + $ picocom -b 115200 /dev/ttyUSB0i > + => loady > + ## Ready for binary (ymodem) download to 0x80000000 at 115200 bps... > + C > + *** file: hello_world.img > + $ sz -vv hello_world.img > + Sending: hello_world.img > + Bytes Sent: 4992 BPS:665 > + Sending: > + Ymodem sectors/kbytes sent: 0/ 0k > + Transfer complete > + > + *** exit status: 0 *** > + CAN) packets, 3 retries > + ## Total Size = 0x00001338 = 4920 Bytes > + => bootm > + ## Booting kernel from Legacy Image at 80000000 ... > + Image Name: > + Image Type: RISC-V U-Boot Standalone Program (uncompressed) > + Data Size: 4856 Bytes = 4.7 KiB > + Load Address: 80000000 > + Entry Point: 80000000 > + Verifying Checksum ... OK > + Loading Standalone Program > + Example expects ABI version 9 > + Actual U-Boot ABI version 9 > + Hello World > + argc = 0 > + argv[0] = "<NULL>" > + Hit any key to exit ... > + > +Over- and Under-clocking > +------------------------ > + > +To change the clock speed of the K210, you will need to enable > +``CONFIG_CLK_K210_SET_RATE`` and edit the board's device tree. To do this, add a > +section to ``arch/riscv/arch/riscv/dts/k210-maix-bit.dts`` like the following: > + > +.. code-block:: > + > + &sysclk { > + assigned-clocks = <&sysclk K210_CLK_PLL0>; > + assigned-clock-rates = <800000000>; > + }; > + > +There are three PLLs on the K210: PLL0 is the parent of most of the components, > +including the CPU and RAM. PLL1 is the parent of the neural network coprocessor. > +PLL2 is the parent of the sound processing devices. Note that child clocks of > +PLL0 and PLL2 run at *half* the speed of the PLLs. For example, if PLL0 is > +running at 800 MHz, then the CPU will run at 400 MHz. This is the example given > +above. The CPU can be overclocked to around 600 MHz, and underclocked to 26 MHz. > + > +It is possible to set PLL2's parent to PLL0. The plls are more accurate when > +converting between similar frequencies. This makes it easier to get an accurate > +frequency for I2S. As an example, consider sampling an I2S device at 44.1 kHz. > +On this device, the I2S serial clock runs at 64 times the sample rate. > +Therefore, we would like to run PLL2 at an even multiple of 2.8224 MHz. If > +PLL2's parent is IN0, we could use a frequency of 390 MHz (the same as the CPU's > +default speed). Dividing by 138 yields a serial clock of about 2.8261 MHz. This > +results in a sample rate of 44.158 kHz---around 50 Hz or .1% too fast. If, > +instead, we set PLL2's parent to PLL1 running at 390 MHz, and request a rate of > +2.8224 * 136 = 383.8464 MHz, the achieved rate is 383.90625 MHz. Dividing by 136 > +yields a serial clock of about 2.8228 MHz. This results in a sample rate of > +44.107 kHz---just 7 Hz or .02% too fast. This configuration is shown in the > +following example: > + > +.. code-block:: > + > + &sysclk { > + assigned-clocks = <&sysclk K210_CLK_PLL1>, <&sysclk K210_CLK_PLL2>; > + assigned-clock-parents = <0>, <&sysclk K210_CLK_PLL1>; > + assigned-clock-rates = <390000000>, <383846400>; > + }; > + > +There are a couple of quirks to the PLLs. First, there are more frequency ratios > +just above and below 1.0, but there is a small gap around 1.0. To be explicit, > +if the input frequency is 100 MHz, it would be impossible to have an output of > +99 or 101 MHz. In addition, there is a maximum frequency for the internal VCO, > +so higher input/output frequencies will be less accurate than lower ones. > + > +Technical Details > +----------------- > + > +Boot Sequence > +^^^^^^^^^^^^^ > + > +1. ``RESET`` pin is deasserted. > +2. Both harts begin executing at ``0x00001000``. > +3. Both harts jump to firmware at ``0x88000000``. > +4. One hart is chosen as a boot hart. > +5. Firmware reads value of pin ``IO_16`` (ISP). > + > + * If the pin is low, enter ISP mode. This mode allows loading data to ram, > + writing it to flash, and booting from specific addresses. > + * If the pin is high, continue boot. > +6. Firmware reads the next stage from flash (SPI3) to address ``0x80000000``. > + > + * If byte 0 is 1, the next stage is decrypted using the built-in AES > + accelerator and the one-time programmable, 128-bit AES key. > + * Bytes 1 to 4 hold the length of the next stage. > + * The SHA-256 sum of the next stage is automatically calculated, and verified > + against the 32 bytes following the next stage. > +7. The boot hart sends an IPI to the other hart telling it to jump to the next > + stage. > +8. The boot hart jumps to ``0x80000000``. > + > +Memory Map > +^^^^^^^^^^ > + > +========== ========= =========== > +Address Size Description > +========== ========= =========== > +0x00000000 0x1000 debug > +0x00001000 0x1000 rom > +0x02000000 0x1000 clint > +0x0C000000 0x4000000 plic > +0x38000000 0x1000 uarths > +0x38001000 0x1000 gpiohs > +0x40000000 0x400000 sram0 (non-cached) > +0x40400000 0x200000 sram1 (non-cached) > +0x40600000 0x200000 airam (non-cached) > +0x40800000 0xC00000 kpu > +0x42000000 0x400000 fft > +0x50000000 0x1000 dmac > +0x50200000 0x200000 apb0 > +0x50200000 0x80 gpio > +0x50210000 0x100 uart0 > +0x50220000 0x100 uart1 > +0x50230000 0x100 uart2 > +0x50240000 0x100 spi slave > +0x50250000 0x200 i2s0 > +0x50250200 0x200 apu > +0x50260000 0x200 i2s1 > +0x50270000 0x200 i2s2 > +0x50280000 0x100 i2c0 > +0x50290000 0x100 i2c1 > +0x502A0000 0x100 i2c2 > +0x502B0000 0x100 fpioa > +0x502C0000 0x100 sha256 > +0x502D0000 0x100 timer0 > +0x502E0000 0x100 timer1 > +0x502F0000 0x100 timer2 > +0x50400000 0x200000 apb1 > +0x50400000 0x100 wdt0 > +0x50410000 0x100 wdt1 > +0x50420000 0x100 otp control > +0x50430000 0x100 dvp > +0x50440000 0x100 sysctl > +0x50450000 0x100 aes > +0x50460000 0x100 rtc > +0x52000000 0x4000000 apb2 > +0x52000000 0x100 spi0 > +0x53000000 0x100 spi1 > +0x54000000 0x200 spi3 > +0x80000000 0x400000 sram0 (cached) > +0x80400000 0x200000 sram1 (cached) > +0x80600000 0x200000 airam (cached) > +0x88000000 0x20000 otp > +0x88000000 0xC200 firmware > +0x8801C000 0x1000 riscv priv spec 1.9 config > +0x8801D000 0x2000 flattened device tree (contains only addresses and > + interrupts) > +0x8801f000 0x1000 credits > +========== ========= =========== > diff --git a/include/configs/sipeed-maix.h b/include/configs/sipeed-maix.h > new file mode 100644 > index 0000000000..a46473fc78 > --- /dev/null > +++ b/include/configs/sipeed-maix.h > @@ -0,0 +1,24 @@ > +/* SPDX-License-Identifier: GPL-2.0+ */ > +/* > + * Copyright (C) 2019-20 Sean Anderson <seanga2 at gmail.com> > + */ > + > +#ifndef CONFIGS_SIPEED_MAIX_H > +#define CONFIGS_SIPEED_MAIX_H > + > +#include <linux/sizes.h> > + > +#define CONFIG_SYS_LOAD_ADDR 0x80000000 > +/* Start just below the second bank so we don't clobber it during reloc */ > +#define CONFIG_SYS_INIT_SP_ADDR 0x803FFFFF > +#define CONFIG_SYS_MALLOC_LEN SZ_128K > +#define CONFIG_SYS_CACHELINE_SIZE 64 > + > +#define CONFIG_SYS_SDRAM_BASE 0x80000000 > +/* Don't relocate into AI ram since it isn't set up yet */ > +#define CONFIG_SYS_SDRAM_SIZE (SZ_4M + SZ_2M) > + > +/* For early init */ > +#define K210_SYSCTL_BASE 0x50440000 > + > +#endif /* CONFIGS_SIPEED_MAIX_H */ > -- > 2.25.0 >
On 3/10/20 5:04 AM, Rick Chen wrote: > Hi Sean > >> The Sipeed Maix series is a collection of boards built around the RISC-V >> Kendryte K210 processor. This processor contains several peripherals to >> accelerate neural network processing and other "ai" tasks. This includes a >> "KPU" neural network processor, an audio processor supporting beamforming >> reception, and a digital video port supporting capture and output at VGA >> resolution. Other peripherals include 8M of sram (accessible with and >> without caching); remappable pins, including 40 GPIOs; AES, FFT, and SHA256 >> accelerators; a DMA controller; and I2C, I2S, and SPI controllers. Maix >> peripherals vary, but include spi flash; on-board usb-serial bridges; ports >> for cameras, displays, and sd cards; and ESP32 chips. Currently, only the >> Sipeed Maix Bit V2.0 (bitm) is supported, but the boards are fairly >> similar. >> >> Documentation for Maix boards is located at >> <http://dl.sipeed.com/MAIX/HDK/>. Documentation for the Kendryte K210 is >> located at <https://kendryte.com/downloads/>. However, hardware details are >> rather lacking, so most technical reference has been taken from the >> standalone sdk located at >> <https://github.com/kendryte/kendryte-standalone-sdk>. >> >> Signed-off-by: Sean Anderson <seanga2 at gmail.com> >> --- > > This patch applying fail > > Applying: riscv: Add Sipeed Maix support > error: patch failed: doc/board/index.rst:16 > error: doc/board/index.rst: patch does not apply > Patch failed at 0001 riscv: Add Sipeed Maix support > The copy of the patch that failed is found in: .git/rebase-apply/patch > When you have resolved this problem, run "git am --continue". > If you prefer to skip this patch, run "git am --skip" instead. > To restore the original branch and stop patching, run "git am --abort". > > I have replied to you the same result in v5 > [v5,33/33] riscv: Add Sipeed Maix support > https://patchwork.ozlabs.org/patch/1246869/#2376311 As above, I just rebased against u-boot/master. I'm not sure what's causing the problem here. > > By the way, > you can not mix them (arch, board, configs, doc)together in a patch. > arch/riscv/Kconfig > board/sipeed/maix/ ... > configs/sipeed_maix_bitm_defconfig > doc/board/index.rst Is there a preferred order for adding these? I will split them for v7. > Thanks, > Rick
Hi Sean > On 3/10/20 5:04 AM, Rick Chen wrote: > > Hi Sean > > > >> The Sipeed Maix series is a collection of boards built around the RISC-V > >> Kendryte K210 processor. This processor contains several peripherals to > >> accelerate neural network processing and other "ai" tasks. This includes a > >> "KPU" neural network processor, an audio processor supporting beamforming > >> reception, and a digital video port supporting capture and output at VGA > >> resolution. Other peripherals include 8M of sram (accessible with and > >> without caching); remappable pins, including 40 GPIOs; AES, FFT, and SHA256 > >> accelerators; a DMA controller; and I2C, I2S, and SPI controllers. Maix > >> peripherals vary, but include spi flash; on-board usb-serial bridges; ports > >> for cameras, displays, and sd cards; and ESP32 chips. Currently, only the > >> Sipeed Maix Bit V2.0 (bitm) is supported, but the boards are fairly > >> similar. > >> > >> Documentation for Maix boards is located at > >> <http://dl.sipeed.com/MAIX/HDK/>. Documentation for the Kendryte K210 is > >> located at <https://kendryte.com/downloads/>. However, hardware details are > >> rather lacking, so most technical reference has been taken from the > >> standalone sdk located at > >> <https://github.com/kendryte/kendryte-standalone-sdk>. > >> > >> Signed-off-by: Sean Anderson <seanga2 at gmail.com> > >> --- > > > > This patch applying fail > > > > Applying: riscv: Add Sipeed Maix support > > error: patch failed: doc/board/index.rst:16 > > error: doc/board/index.rst: patch does not apply > > Patch failed at 0001 riscv: Add Sipeed Maix support > > The copy of the patch that failed is found in: .git/rebase-apply/patch > > When you have resolved this problem, run "git am --continue". > > If you prefer to skip this patch, run "git am --skip" instead. > > To restore the original branch and stop patching, run "git am --abort". > > > > I have replied to you the same result in v5 > > [v5,33/33] riscv: Add Sipeed Maix support > > https://patchwork.ozlabs.org/patch/1246869/#2376311 > > As above, I just rebased against u-boot/master. I'm not sure what's > causing the problem here. > > > > > By the way, > > you can not mix them (arch, board, configs, doc)together in a patch. > > arch/riscv/Kconfig > > board/sipeed/maix/ ... > > configs/sipeed_maix_bitm_defconfig > > doc/board/index.rst > > Is there a preferred order for adding these? I will split them for v7. Maybe you can group them as two patchs patch 19/20 arch/riscv/Kconfig board/sipeed/maix/Kconfig board/sipeed/maix/MAINTAINERS board/sipeed/maix/Makefile board/sipeed/maix/maix.c configs/sipeed_maix_bitm_defconfig include/configs/sipeed-maix.h patch 19/20 doc/board/index.rst doc/board/sipeed/index.rst doc/board/sipeed/maix.rst Thanks, Rick > > > Thanks, > > Rick >
diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig index b7a5757584..d016dd75d7 100644 --- a/arch/riscv/Kconfig +++ b/arch/riscv/Kconfig @@ -20,6 +20,9 @@ config TARGET_QEMU_VIRT config TARGET_SIFIVE_FU540 bool "Support SiFive FU540 Board" +config TARGET_SIPEED_MAIX + bool "Support Sipeed Maix Board" + endchoice config SYS_ICACHE_OFF @@ -53,6 +56,7 @@ source "board/AndesTech/ax25-ae350/Kconfig" source "board/emulation/qemu-riscv/Kconfig" source "board/microchip/mpfs_icicle/Kconfig" source "board/sifive/fu540/Kconfig" +source "board/sipeed/maix/Kconfig" # platform-specific options below source "arch/riscv/cpu/ax25/Kconfig" diff --git a/board/sipeed/maix/Kconfig b/board/sipeed/maix/Kconfig new file mode 100644 index 0000000000..8292089fc9 --- /dev/null +++ b/board/sipeed/maix/Kconfig @@ -0,0 +1,48 @@ +# SPDX-License-Identifier: GPL-2.0+ +# Copyright (C) 2019-20 Sean Anderson <seanga2 at gmail.com> + +if TARGET_SIPEED_MAIX + +config SYS_BOARD + default "maix" + +config SYS_VENDOR + default "sipeed" + +config SYS_CPU + default "generic" + +config SYS_CONFIG_NAME + default "sipeed-maix" + +config SYS_TEXT_BASE + default 0x80000000 + +config DEFAULT_DEVICE_TREE + default "k210-maix-bit" + +config NR_CPUS + default 2 + +config NR_DRAM_BANKS + default 3 + +config BOARD_SPECIFIC_OPTIONS + def_bool y + select GENERIC_RISCV + select RISCV_PRIV_1_9 + imply SMP + imply OF_BOARD_SETUP + imply DM_SERIAL + imply SIFIVE_SERIAL + imply SIFIVE_CLINT + imply POWER_DOMAIN + imply SIMPLE_PM_BUS + imply CLK_CCF + imply CLK_COMPOSITE_CCF + imply CLK_K210 + imply DM_RESET + imply RESET_SYSCON + imply SYSRESET + imply SYSRESET_SYSCON +endif diff --git a/board/sipeed/maix/MAINTAINERS b/board/sipeed/maix/MAINTAINERS new file mode 100644 index 0000000000..1f33882e1e --- /dev/null +++ b/board/sipeed/maix/MAINTAINERS @@ -0,0 +1,11 @@ +Sipeed Maix BOARD +M: Sean Anderson <seanga2 at gmail.com> +S: Maintained +F: arch/riscv/dts/k210.dtsi +F: arch/riscv/dts/k210-maix-bit.dts +F: board/sipeed/maix/ +F: configs/sipeed_maix_defconfig +F: doc/board/sipeed/ +F: include/configs/sipeed-maix.h +F: include/dt-bindings/*/k210-sysctl.h +F: test/dm/k210_pll.c diff --git a/board/sipeed/maix/Makefile b/board/sipeed/maix/Makefile new file mode 100644 index 0000000000..4acff5b31e --- /dev/null +++ b/board/sipeed/maix/Makefile @@ -0,0 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# Copyright (c) 2019 Western Digital Corporation or its affiliates. + +obj-y += maix.o diff --git a/board/sipeed/maix/maix.c b/board/sipeed/maix/maix.c new file mode 100644 index 0000000000..c126cb5d67 --- /dev/null +++ b/board/sipeed/maix/maix.c @@ -0,0 +1,54 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2019 Sean Anderson <seanga2 at gmail.com> + */ + +#include <common.h> +#include <clk.h> +#include <dm.h> +#include <fdt_support.h> + +phys_size_t get_effective_memsize(void) +{ + return CONFIG_SYS_SDRAM_SIZE; +} + +int board_init(void) +{ + int ret; + ofnode bank = ofnode_null(); + + /* Enable RAM clocks */ + while (true) { + struct clk clk; + + bank = ofnode_by_prop_value(bank, "device_type", "memory", + sizeof("memory")); + if (ofnode_equal(bank, ofnode_null())) + break; + + ret = clk_get_by_index_nodev(bank, 0, &clk); + if (ret) + continue; + + ret = clk_enable(&clk); + clk_free(&clk); + if (ret) + return ret; + } + return 0; +} + +int ft_board_setup(void *blob, bd_t *bd) +{ + int i; + u64 base[CONFIG_NR_DRAM_BANKS]; + u64 size[CONFIG_NR_DRAM_BANKS]; + + for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) { + base[i] = bd->bi_dram[i].start; + size[i] = bd->bi_dram[i].size; + } + + return fdt_fixup_memory_banks(blob, base, size, CONFIG_NR_DRAM_BANKS); +} diff --git a/configs/sipeed_maix_bitm_defconfig b/configs/sipeed_maix_bitm_defconfig new file mode 100644 index 0000000000..f48f7f06e9 --- /dev/null +++ b/configs/sipeed_maix_bitm_defconfig @@ -0,0 +1,8 @@ +CONFIG_RISCV=y +CONFIG_TARGET_SIPEED_MAIX=y +CONFIG_ARCH_RV64I=y +CONFIG_SYS_REDUNDAND_ENVIRONMENT=y +# CONFIG_NET is not set +# CONFIG_INPUT is not set +# CONFIG_DM_ETH is not set +# CONFIG_EFI_LOADER is not set diff --git a/doc/board/index.rst b/doc/board/index.rst index d43e536ca3..94f01bb098 100644 --- a/doc/board/index.rst +++ b/doc/board/index.rst @@ -16,5 +16,6 @@ Board-specific doc renesas/index rockchip/index sifive/index + sipeed/index st/index xilinx/index diff --git a/doc/board/sipeed/index.rst b/doc/board/sipeed/index.rst new file mode 100644 index 0000000000..3518e2d8f4 --- /dev/null +++ b/doc/board/sipeed/index.rst @@ -0,0 +1,9 @@ +.. SPDX-License-Identifier: GPL-2.0+ + +Sipeed +====== + +.. toctree:: + :maxdepth: 2 + + maix diff --git a/doc/board/sipeed/maix.rst b/doc/board/sipeed/maix.rst new file mode 100644 index 0000000000..b11ee0182e --- /dev/null +++ b/doc/board/sipeed/maix.rst @@ -0,0 +1,298 @@ +.. SPDX-License-Identifier: GPL-2.0+ +.. Copyright (C) 2020 Sean Anderson <seanga2 at gmail.com> + +Maix Bit +======== + +Several of the Sipeed Maix series of boards cotain the Kendryte K210 processor, +a 64-bit RISC-V CPU. This processor contains several peripherals to accelerate +neural network processing and other "ai" tasks. This includes a "KPU" neural +network processor, an audio processor supporting beamforming reception, and a +digital video port supporting capture and output at VGA resolution. Other +peripherals include 8M of SRAM (accessible with and without caching); remappable +pins, including 40 GPIOs; AES, FFT, and SHA256 accelerators; a DMA controller; +and I2C, I2S, and SPI controllers. Maix peripherals vary, but include spi flash; +on-board usb-serial bridges; ports for cameras, displays, and sd cards; and +ESP32 chips. Currently, only the Sipeed Maix Bit V2.0 (bitm) is supported, but +the boards are fairly similar. + +Documentation for Maix boards is available from +`Sipeed's website <http://dl.sipeed.com/MAIX/HDK/>`_. +Documentation for the Kendryte K210 is available from +`Kendryte's website <https://kendryte.com/downloads/>`_. However, hardware +details are rather lacking, so most technical reference has been taken from the +`standalone sdk <https://github.com/kendryte/kendryte-standalone-sdk>`_. + +Build and boot steps +-------------------- + +To build u-boot, run + +.. code-block:: none + + make sipeed_maix_bitm_defconfig + make CROSS_COMPILE=<your cross compile prefix> + +To flash u-boot to a maix bit, run + +.. code-block:: none + + kflash -tp /dev/<your tty here> -B bit_mic u-boot-dtb.bin + +Boot output should look like the following: + +.. code-block:: none + + U-Boot 2020.04-rc2-00087-g2221cc09c1-dirty (Feb 28 2020 - 13:53:09 -0500) + + DRAM: 8 MiB + In: serial at 38000000 + Out: serial at 38000000 + Err: serial at 38000000 + => + +Loading Images +^^^^^^^^^^^^^^ + +To load a kernel, transfer it over serial. + +.. code-block:: none + + => loady 80000000 1500000 + ## Switch baudrate to 1500000 bps and press ENTER ... + + *** baud: 1500000 + + *** baud: 1500000 *** + ## Ready for binary (ymodem) download to 0x80000000 at 1500000 bps... + C + *** file: loader.bin + $ sz -vv loader.bin + Sending: loader.bin + Bytes Sent:2478208 BPS:72937 + Sending: + Ymodem sectors/kbytes sent: 0/ 0k + Transfer complete + + *** exit status: 0 *** + ## Total Size = 0x0025d052 = 2478162 Bytes + ## Switch baudrate to 115200 bps and press ESC ... + + *** baud: 115200 + + *** baud: 115200 *** + => + +Running Programs +^^^^^^^^^^^^^^^^ + +Binaries +"""""""" + +To run a bare binary, use the ``go`` command: + +.. code-block:: none + + => loady + ## Ready for binary (ymodem) download to 0x80000000 at 115200 bps... + C + *** file: ./examples/standalone/hello_world.bin + $ sz -vv ./examples/standalone/hello_world.bin + Sending: hello_world.bin + Bytes Sent: 4864 BPS:649 + Sending: + Ymodem sectors/kbytes sent: 0/ 0k + Transfer complete + + *** exit status: 0 *** + (CAN) packets, 5 retries + ## Total Size = 0x000012f8 = 4856 Bytes + => go 80000000 + ## Starting application at 0x80000000 ... + Example expects ABI version 9 + Actual U-Boot ABI version 9 + Hello World + argc = 1 + argv[0] = "80000000" + argv[1] = "<NULL>" + Hit any key to exit ... + +Legacy Images +""""""""""""" + +To run legacy images, use the ``bootm`` command: + +.. code-block:: none + + $ tools/mkimage -A riscv -O u-boot -T standalone -C none -a 80000000 -e 80000000 -d examples/standalone/hello_world.bin hello_world.img + Image Name: + Created: Thu Mar 5 12:04:10 2020 + Image Type: RISC-V U-Boot Standalone Program (uncompressed) + Data Size: 4856 Bytes = 4.74 KiB = 0.00 MiB + Load Address: 80000000 + Entry Point: 80000000 + + $ picocom -b 115200 /dev/ttyUSB0i + => loady + ## Ready for binary (ymodem) download to 0x80000000 at 115200 bps... + C + *** file: hello_world.img + $ sz -vv hello_world.img + Sending: hello_world.img + Bytes Sent: 4992 BPS:665 + Sending: + Ymodem sectors/kbytes sent: 0/ 0k + Transfer complete + + *** exit status: 0 *** + CAN) packets, 3 retries + ## Total Size = 0x00001338 = 4920 Bytes + => bootm + ## Booting kernel from Legacy Image at 80000000 ... + Image Name: + Image Type: RISC-V U-Boot Standalone Program (uncompressed) + Data Size: 4856 Bytes = 4.7 KiB + Load Address: 80000000 + Entry Point: 80000000 + Verifying Checksum ... OK + Loading Standalone Program + Example expects ABI version 9 + Actual U-Boot ABI version 9 + Hello World + argc = 0 + argv[0] = "<NULL>" + Hit any key to exit ... + +Over- and Under-clocking +------------------------ + +To change the clock speed of the K210, you will need to enable +``CONFIG_CLK_K210_SET_RATE`` and edit the board's device tree. To do this, add a +section to ``arch/riscv/arch/riscv/dts/k210-maix-bit.dts`` like the following: + +.. code-block:: + + &sysclk { + assigned-clocks = <&sysclk K210_CLK_PLL0>; + assigned-clock-rates = <800000000>; + }; + +There are three PLLs on the K210: PLL0 is the parent of most of the components, +including the CPU and RAM. PLL1 is the parent of the neural network coprocessor. +PLL2 is the parent of the sound processing devices. Note that child clocks of +PLL0 and PLL2 run at *half* the speed of the PLLs. For example, if PLL0 is +running at 800 MHz, then the CPU will run at 400 MHz. This is the example given +above. The CPU can be overclocked to around 600 MHz, and underclocked to 26 MHz. + +It is possible to set PLL2's parent to PLL0. The plls are more accurate when +converting between similar frequencies. This makes it easier to get an accurate +frequency for I2S. As an example, consider sampling an I2S device at 44.1 kHz. +On this device, the I2S serial clock runs at 64 times the sample rate. +Therefore, we would like to run PLL2 at an even multiple of 2.8224 MHz. If +PLL2's parent is IN0, we could use a frequency of 390 MHz (the same as the CPU's +default speed). Dividing by 138 yields a serial clock of about 2.8261 MHz. This +results in a sample rate of 44.158 kHz---around 50 Hz or .1% too fast. If, +instead, we set PLL2's parent to PLL1 running at 390 MHz, and request a rate of +2.8224 * 136 = 383.8464 MHz, the achieved rate is 383.90625 MHz. Dividing by 136 +yields a serial clock of about 2.8228 MHz. This results in a sample rate of +44.107 kHz---just 7 Hz or .02% too fast. This configuration is shown in the +following example: + +.. code-block:: + + &sysclk { + assigned-clocks = <&sysclk K210_CLK_PLL1>, <&sysclk K210_CLK_PLL2>; + assigned-clock-parents = <0>, <&sysclk K210_CLK_PLL1>; + assigned-clock-rates = <390000000>, <383846400>; + }; + +There are a couple of quirks to the PLLs. First, there are more frequency ratios +just above and below 1.0, but there is a small gap around 1.0. To be explicit, +if the input frequency is 100 MHz, it would be impossible to have an output of +99 or 101 MHz. In addition, there is a maximum frequency for the internal VCO, +so higher input/output frequencies will be less accurate than lower ones. + +Technical Details +----------------- + +Boot Sequence +^^^^^^^^^^^^^ + +1. ``RESET`` pin is deasserted. +2. Both harts begin executing at ``0x00001000``. +3. Both harts jump to firmware at ``0x88000000``. +4. One hart is chosen as a boot hart. +5. Firmware reads value of pin ``IO_16`` (ISP). + + * If the pin is low, enter ISP mode. This mode allows loading data to ram, + writing it to flash, and booting from specific addresses. + * If the pin is high, continue boot. +6. Firmware reads the next stage from flash (SPI3) to address ``0x80000000``. + + * If byte 0 is 1, the next stage is decrypted using the built-in AES + accelerator and the one-time programmable, 128-bit AES key. + * Bytes 1 to 4 hold the length of the next stage. + * The SHA-256 sum of the next stage is automatically calculated, and verified + against the 32 bytes following the next stage. +7. The boot hart sends an IPI to the other hart telling it to jump to the next + stage. +8. The boot hart jumps to ``0x80000000``. + +Memory Map +^^^^^^^^^^ + +========== ========= =========== +Address Size Description +========== ========= =========== +0x00000000 0x1000 debug +0x00001000 0x1000 rom +0x02000000 0x1000 clint +0x0C000000 0x4000000 plic +0x38000000 0x1000 uarths +0x38001000 0x1000 gpiohs +0x40000000 0x400000 sram0 (non-cached) +0x40400000 0x200000 sram1 (non-cached) +0x40600000 0x200000 airam (non-cached) +0x40800000 0xC00000 kpu +0x42000000 0x400000 fft +0x50000000 0x1000 dmac +0x50200000 0x200000 apb0 +0x50200000 0x80 gpio +0x50210000 0x100 uart0 +0x50220000 0x100 uart1 +0x50230000 0x100 uart2 +0x50240000 0x100 spi slave +0x50250000 0x200 i2s0 +0x50250200 0x200 apu +0x50260000 0x200 i2s1 +0x50270000 0x200 i2s2 +0x50280000 0x100 i2c0 +0x50290000 0x100 i2c1 +0x502A0000 0x100 i2c2 +0x502B0000 0x100 fpioa +0x502C0000 0x100 sha256 +0x502D0000 0x100 timer0 +0x502E0000 0x100 timer1 +0x502F0000 0x100 timer2 +0x50400000 0x200000 apb1 +0x50400000 0x100 wdt0 +0x50410000 0x100 wdt1 +0x50420000 0x100 otp control +0x50430000 0x100 dvp +0x50440000 0x100 sysctl +0x50450000 0x100 aes +0x50460000 0x100 rtc +0x52000000 0x4000000 apb2 +0x52000000 0x100 spi0 +0x53000000 0x100 spi1 +0x54000000 0x200 spi3 +0x80000000 0x400000 sram0 (cached) +0x80400000 0x200000 sram1 (cached) +0x80600000 0x200000 airam (cached) +0x88000000 0x20000 otp +0x88000000 0xC200 firmware +0x8801C000 0x1000 riscv priv spec 1.9 config +0x8801D000 0x2000 flattened device tree (contains only addresses and + interrupts) +0x8801f000 0x1000 credits +========== ========= =========== diff --git a/include/configs/sipeed-maix.h b/include/configs/sipeed-maix.h new file mode 100644 index 0000000000..a46473fc78 --- /dev/null +++ b/include/configs/sipeed-maix.h @@ -0,0 +1,24 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2019-20 Sean Anderson <seanga2 at gmail.com> + */ + +#ifndef CONFIGS_SIPEED_MAIX_H +#define CONFIGS_SIPEED_MAIX_H + +#include <linux/sizes.h> + +#define CONFIG_SYS_LOAD_ADDR 0x80000000 +/* Start just below the second bank so we don't clobber it during reloc */ +#define CONFIG_SYS_INIT_SP_ADDR 0x803FFFFF +#define CONFIG_SYS_MALLOC_LEN SZ_128K +#define CONFIG_SYS_CACHELINE_SIZE 64 + +#define CONFIG_SYS_SDRAM_BASE 0x80000000 +/* Don't relocate into AI ram since it isn't set up yet */ +#define CONFIG_SYS_SDRAM_SIZE (SZ_4M + SZ_2M) + +/* For early init */ +#define K210_SYSCTL_BASE 0x50440000 + +#endif /* CONFIGS_SIPEED_MAIX_H */
The Sipeed Maix series is a collection of boards built around the RISC-V Kendryte K210 processor. This processor contains several peripherals to accelerate neural network processing and other "ai" tasks. This includes a "KPU" neural network processor, an audio processor supporting beamforming reception, and a digital video port supporting capture and output at VGA resolution. Other peripherals include 8M of sram (accessible with and without caching); remappable pins, including 40 GPIOs; AES, FFT, and SHA256 accelerators; a DMA controller; and I2C, I2S, and SPI controllers. Maix peripherals vary, but include spi flash; on-board usb-serial bridges; ports for cameras, displays, and sd cards; and ESP32 chips. Currently, only the Sipeed Maix Bit V2.0 (bitm) is supported, but the boards are fairly similar. Documentation for Maix boards is located at <http://dl.sipeed.com/MAIX/HDK/>. Documentation for the Kendryte K210 is located at <https://kendryte.com/downloads/>. However, hardware details are rather lacking, so most technical reference has been taken from the standalone sdk located at <https://github.com/kendryte/kendryte-standalone-sdk>. Signed-off-by: Sean Anderson <seanga2 at gmail.com> --- Changes in v6: - Remove trailing whitespace from documentation - Remove configuration for spi/pinmux/gpio features - Flesh out documentation some more Changes in v5: - Configure relocation location with CONFIG_SYS_SDRAM_* - Enable ram clocks - Add pinmux/gpio/led support - Remove (broken) MMC support - Store the environment in flash - Add partitions - Add bootcmd - Add docs for pinctrl and booting Changes in v4: - Rework documentation to be organized by board mfg not cpu mfg - Update docs to reflect working SPI support - Add proper spi support - Don't define unneecessary macros in config.h - Lower the default stack so it isn't clobbered on relocation - Update MAINTAINERS - Update copyright Changes in v3: - Reorder to be last in the patch series - Add documentation for the board - Generate defconfig with "make savedefconfig" - Update Kconfig to imply most features we need - Update MAINTAINERS Changes in v2: - Select CONFIG_SYS_RISCV_NOCOUNTER - Imply CONFIG_CLK_K210 - Remove spurious references to CONFIG_ARCH_K210 - Remove many configs from defconfig where the defaults were fine - Add a few "not set" lines to suppress unneeded defaults - Reduce pre-reloc malloc space, now that clocks initialization happens later arch/riscv/Kconfig | 4 + board/sipeed/maix/Kconfig | 48 +++++ board/sipeed/maix/MAINTAINERS | 11 ++ board/sipeed/maix/Makefile | 5 + board/sipeed/maix/maix.c | 54 ++++++ configs/sipeed_maix_bitm_defconfig | 8 + doc/board/index.rst | 1 + doc/board/sipeed/index.rst | 9 + doc/board/sipeed/maix.rst | 298 +++++++++++++++++++++++++++++ include/configs/sipeed-maix.h | 24 +++ 10 files changed, 462 insertions(+) create mode 100644 board/sipeed/maix/Kconfig create mode 100644 board/sipeed/maix/MAINTAINERS create mode 100644 board/sipeed/maix/Makefile create mode 100644 board/sipeed/maix/maix.c create mode 100644 configs/sipeed_maix_bitm_defconfig create mode 100644 doc/board/sipeed/index.rst create mode 100644 doc/board/sipeed/maix.rst create mode 100644 include/configs/sipeed-maix.h