diff mbox series

stm32mp: psci: set cntfrq register of cpu on

Message ID 20200302102702.6917-1-patrick.delaunay@st.com
State Accepted
Commit 40e70ab8855f7a846527802a7fe8eec41f6517f8
Headers show
Series stm32mp: psci: set cntfrq register of cpu on | expand

Commit Message

Patrick Delaunay March 2, 2020, 10:27 a.m. UTC
From: Ludovic Barre <ludovic.barre at st.com>

This path allows to set the cntfrq register of targeted cpu.

Signed-off-by: Ludovic Barre <ludovic.barre at st.com>
Reviewed-by: Patrick DELAUNAY <patrick.delaunay at st.com>
Signed-off-by: Patrick Delaunay <patrick.delaunay at st.com>
---

 arch/arm/mach-stm32mp/psci.c | 22 ++++++++++++++++++++++
 1 file changed, 22 insertions(+)

Comments

Patrice CHOTARD March 18, 2020, 9:58 a.m. UTC | #1
On 3/2/20 11:27 AM, Patrick Delaunay wrote:
> From: Ludovic Barre <ludovic.barre at st.com>
>
> This path allows to set the cntfrq register of targeted cpu.
>
> Signed-off-by: Ludovic Barre <ludovic.barre at st.com>
> Reviewed-by: Patrick DELAUNAY <patrick.delaunay at st.com>
> Signed-off-by: Patrick Delaunay <patrick.delaunay at st.com>
> ---
>
>  arch/arm/mach-stm32mp/psci.c | 22 ++++++++++++++++++++++
>  1 file changed, 22 insertions(+)
>
> diff --git a/arch/arm/mach-stm32mp/psci.c b/arch/arm/mach-stm32mp/psci.c
> index 1d91b2d324..3fb038d3e7 100644
> --- a/arch/arm/mach-stm32mp/psci.c
> +++ b/arch/arm/mach-stm32mp/psci.c
> @@ -30,6 +30,22 @@ u8 psci_state[STM32MP1_PSCI_NR_CPUS] __secure_data = {
>  	 PSCI_AFFINITY_LEVEL_ON,
>  	 PSCI_AFFINITY_LEVEL_OFF};
>  
> +static u32 __secure_data cntfrq;
> +
> +static u32 __secure cp15_read_cntfrq(void)
> +{
> +	u32 frq;
> +
> +	asm volatile("mrc p15, 0, %0, c14, c0, 0" : "=r" (frq));
> +
> +	return frq;
> +}
> +
> +static void __secure cp15_write_cntfrq(u32 frq)
> +{
> +	asm volatile ("mcr p15, 0, %0, c14, c0, 0" : : "r" (frq));
> +}
> +
>  static inline void psci_set_state(int cpu, u8 state)
>  {
>  	psci_state[cpu] = state;
> @@ -63,6 +79,9 @@ void __secure psci_arch_cpu_entry(void)
>  
>  	psci_set_state(cpu, PSCI_AFFINITY_LEVEL_ON);
>  
> +	/* write the saved cntfrq */
> +	cp15_write_cntfrq(cntfrq);
> +
>  	/* reset magic in TAMP register */
>  	writel(0xFFFFFFFF, TAMP_BACKUP_MAGIC_NUMBER);
>  }
> @@ -130,6 +149,9 @@ s32 __secure psci_cpu_on(u32 function_id, u32 target_cpu, u32 pc,
>  	if (psci_state[cpu] == PSCI_AFFINITY_LEVEL_ON)
>  		return ARM_PSCI_RET_ALREADY_ON;
>  
> +	/* read and save cntfrq of current cpu to write on target cpu  */
> +	cntfrq = cp15_read_cntfrq();
> +
>  	/* reset magic in TAMP register */
>  	if (readl(TAMP_BACKUP_MAGIC_NUMBER))
>  		writel(0xFFFFFFFF, TAMP_BACKUP_MAGIC_NUMBER);

Acked-by: Patrice Chotard <patrice.chotard at st.com>

Thanks

PAtrice
Patrick Delaunay March 24, 2020, 8:42 a.m. UTC | #2
Hi,

> From: Patrick DELAUNAY <patrick.delaunay at st.com>
> Sent: lundi 2 mars 2020 11:27
> 
> From: Ludovic Barre <ludovic.barre at st.com>
> 
> This path allows to set the cntfrq register of targeted cpu.
> 
> Signed-off-by: Ludovic Barre <ludovic.barre at st.com>
> Reviewed-by: Patrick DELAUNAY <patrick.delaunay at st.com>
> Signed-off-by: Patrick Delaunay <patrick.delaunay at st.com>
> ---

Applied to u-boot-stm/next, thanks!

Regards

Patrick
diff mbox series

Patch

diff --git a/arch/arm/mach-stm32mp/psci.c b/arch/arm/mach-stm32mp/psci.c
index 1d91b2d324..3fb038d3e7 100644
--- a/arch/arm/mach-stm32mp/psci.c
+++ b/arch/arm/mach-stm32mp/psci.c
@@ -30,6 +30,22 @@  u8 psci_state[STM32MP1_PSCI_NR_CPUS] __secure_data = {
 	 PSCI_AFFINITY_LEVEL_ON,
 	 PSCI_AFFINITY_LEVEL_OFF};
 
+static u32 __secure_data cntfrq;
+
+static u32 __secure cp15_read_cntfrq(void)
+{
+	u32 frq;
+
+	asm volatile("mrc p15, 0, %0, c14, c0, 0" : "=r" (frq));
+
+	return frq;
+}
+
+static void __secure cp15_write_cntfrq(u32 frq)
+{
+	asm volatile ("mcr p15, 0, %0, c14, c0, 0" : : "r" (frq));
+}
+
 static inline void psci_set_state(int cpu, u8 state)
 {
 	psci_state[cpu] = state;
@@ -63,6 +79,9 @@  void __secure psci_arch_cpu_entry(void)
 
 	psci_set_state(cpu, PSCI_AFFINITY_LEVEL_ON);
 
+	/* write the saved cntfrq */
+	cp15_write_cntfrq(cntfrq);
+
 	/* reset magic in TAMP register */
 	writel(0xFFFFFFFF, TAMP_BACKUP_MAGIC_NUMBER);
 }
@@ -130,6 +149,9 @@  s32 __secure psci_cpu_on(u32 function_id, u32 target_cpu, u32 pc,
 	if (psci_state[cpu] == PSCI_AFFINITY_LEVEL_ON)
 		return ARM_PSCI_RET_ALREADY_ON;
 
+	/* read and save cntfrq of current cpu to write on target cpu  */
+	cntfrq = cp15_read_cntfrq();
+
 	/* reset magic in TAMP register */
 	if (readl(TAMP_BACKUP_MAGIC_NUMBER))
 		writel(0xFFFFFFFF, TAMP_BACKUP_MAGIC_NUMBER);