diff mbox series

[v2,4/5] mips: cache: Make invalidate_dcache_range() weak to enable overwrite

Message ID 20200630103320.1290545-5-sr@denx.de
State Accepted
Commit 60a0559b7fe9bdb9433dc39c42e3e12c4363d63e
Headers show
Series mips: Improve initial Octeon MIPS64 support | expand

Commit Message

Stefan Roese June 30, 2020, 10:33 a.m. UTC 
This patch adds __weak to invalidate_dcache_range() in lib/cache.c. This
makes it possible to overwrite this function by a platforms specific
version, which will be done for Octeon.

Signed-off-by: Stefan Roese <sr at denx.de>
---

(no changes since v1)

 arch/mips/lib/cache.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)
diff mbox series

Patch

diff --git a/arch/mips/lib/cache.c b/arch/mips/lib/cache.c
index ad37f05802..cf29994a7a 100644
--- a/arch/mips/lib/cache.c
+++ b/arch/mips/lib/cache.c
@@ -159,7 +159,7 @@  void __weak flush_dcache_range(ulong start_addr, ulong stop)
 	sync();
 }
 
-void invalidate_dcache_range(ulong start_addr, ulong stop)
+void __weak invalidate_dcache_range(ulong start_addr, ulong stop)
 {
 	unsigned long lsize = dcache_line_size();
 	unsigned long slsize = scache_line_size();