Message ID | 20200623095141.3310591-6-sr@denx.de |
---|---|
State | Superseded |
Headers | show |
Series | mips: Improve initial Octeon MIPS64 support | expand |
diff --git a/arch/mips/mach-octeon/cache.c b/arch/mips/mach-octeon/cache.c index bea846d757..9a88bb97c7 100644 --- a/arch/mips/mach-octeon/cache.c +++ b/arch/mips/mach-octeon/cache.c @@ -18,3 +18,7 @@ void flush_dcache_range(ulong start_addr, ulong stop) void flush_cache(ulong start_addr, ulong size) { } + +void invalidate_dcache_range(ulong start_addr, ulong stop) +{ +}
As Octeon is cache coherent, lets add an empty version of invalidate_dcache_range(). With this, all global cache functions are replaced by no-ops on Octeon. Signed-off-by: Stefan Roese <sr at denx.de> --- arch/mips/mach-octeon/cache.c | 4 ++++ 1 file changed, 4 insertions(+)