| Message ID | 20200622131710.31168-3-al.kochet@gmail.com |
|---|---|
| State | New |
| Headers | show |
| Series | v2: rr3188: change APP to 600MHz and enable bwadj for DPLL | expand |
Hi Alex, ??? I think it will be better to update the rk3188_clk_probe() function instead of what you have modified if the RK3188 and RK3188A has the same PLL(I'm not sure about it now). Thanks, - Kever On 2020/6/22 ??9:17, Alexander Kochetkov wrote: > Empirically, I found that DPLL on rk3188 has bwadj registers. > Configuring DPLL with bwadj increase DPLL stability. Because > of DPLL provide clock for ethernet, enabling bwaj reduces > the number of errors on the ethernet. > > Signed-off-by: Alexander Kochetkov <al.kochet at gmail.com> > --- > drivers/clk/rockchip/clk_rk3188.c | 8 ++++---- > 1 file changed, 4 insertions(+), 4 deletions(-) > > diff --git a/drivers/clk/rockchip/clk_rk3188.c b/drivers/clk/rockchip/clk_rk3188.c > index 4fc5c78563..ee5782d25d 100644 > --- a/drivers/clk/rockchip/clk_rk3188.c > +++ b/drivers/clk/rockchip/clk_rk3188.c > @@ -117,7 +117,7 @@ static int rkclk_set_pll(struct rk3188_cru *cru, enum rk_clk_id clk_id, > } > > static int rkclk_configure_ddr(struct rk3188_cru *cru, struct rk3188_grf *grf, > - unsigned int hz, bool has_bwadj) > + unsigned int hz) > { > static const struct pll_div dpll_cfg[] = { > {.nf = 75, .nr = 1, .no = 6}, > @@ -149,7 +149,8 @@ static int rkclk_configure_ddr(struct rk3188_cru *cru, struct rk3188_grf *grf, > rk_clrsetreg(&cru->cru_mode_con, DPLL_MODE_MASK << DPLL_MODE_SHIFT, > DPLL_MODE_SLOW << DPLL_MODE_SHIFT); > > - rkclk_set_pll(cru, CLK_DDR, &dpll_cfg[cfg], has_bwadj); > + /* rk3188 and rk3188a DPLL has bwadj */ > + rkclk_set_pll(cru, CLK_DDR, &dpll_cfg[cfg], 1); > > /* wait for pll lock */ > while (!(readl(&grf->soc_status0) & SOCSTS_DPLL_LOCK)) > @@ -504,8 +505,7 @@ static ulong rk3188_clk_set_rate(struct clk *clk, ulong rate) > priv->has_bwadj); > break; > case CLK_DDR: > - new_rate = rkclk_configure_ddr(priv->cru, priv->grf, rate, > - priv->has_bwadj); > + new_rate = rkclk_configure_ddr(priv->cru, priv->grf, rate); > break; > case HCLK_EMMC: > case HCLK_SDMMC:
diff --git a/drivers/clk/rockchip/clk_rk3188.c b/drivers/clk/rockchip/clk_rk3188.c index 4fc5c78563..ee5782d25d 100644 --- a/drivers/clk/rockchip/clk_rk3188.c +++ b/drivers/clk/rockchip/clk_rk3188.c @@ -117,7 +117,7 @@ static int rkclk_set_pll(struct rk3188_cru *cru, enum rk_clk_id clk_id, } static int rkclk_configure_ddr(struct rk3188_cru *cru, struct rk3188_grf *grf, - unsigned int hz, bool has_bwadj) + unsigned int hz) { static const struct pll_div dpll_cfg[] = { {.nf = 75, .nr = 1, .no = 6}, @@ -149,7 +149,8 @@ static int rkclk_configure_ddr(struct rk3188_cru *cru, struct rk3188_grf *grf, rk_clrsetreg(&cru->cru_mode_con, DPLL_MODE_MASK << DPLL_MODE_SHIFT, DPLL_MODE_SLOW << DPLL_MODE_SHIFT); - rkclk_set_pll(cru, CLK_DDR, &dpll_cfg[cfg], has_bwadj); + /* rk3188 and rk3188a DPLL has bwadj */ + rkclk_set_pll(cru, CLK_DDR, &dpll_cfg[cfg], 1); /* wait for pll lock */ while (!(readl(&grf->soc_status0) & SOCSTS_DPLL_LOCK)) @@ -504,8 +505,7 @@ static ulong rk3188_clk_set_rate(struct clk *clk, ulong rate) priv->has_bwadj); break; case CLK_DDR: - new_rate = rkclk_configure_ddr(priv->cru, priv->grf, rate, - priv->has_bwadj); + new_rate = rkclk_configure_ddr(priv->cru, priv->grf, rate); break; case HCLK_EMMC: case HCLK_SDMMC:
Empirically, I found that DPLL on rk3188 has bwadj registers. Configuring DPLL with bwadj increase DPLL stability. Because of DPLL provide clock for ethernet, enabling bwaj reduces the number of errors on the ethernet. Signed-off-by: Alexander Kochetkov <al.kochet at gmail.com> --- drivers/clk/rockchip/clk_rk3188.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-)