| Message ID | 20200618211625.31135-3-festevam@gmail.com |
|---|---|
| State | Superseded |
| Headers | show |
| Series | [v2,1/4] phy: atheros: ar8035: Fix clock output calculation | expand |
diff --git a/arch/arm/dts/imx6qdl-sr-som.dtsi b/arch/arm/dts/imx6qdl-sr-som.dtsi index 6d7f6b9035..b06577808f 100644 --- a/arch/arm/dts/imx6qdl-sr-som.dtsi +++ b/arch/arm/dts/imx6qdl-sr-som.dtsi @@ -53,10 +53,21 @@ &fec { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_microsom_enet_ar8035>; + phy-handle = <&phy>; phy-mode = "rgmii-id"; phy-reset-duration = <2>; phy-reset-gpios = <&gpio4 15 GPIO_ACTIVE_LOW>; status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + phy: ethernet-phy at 0 { + reg = <0>; + qca,clk-out-frequency = <125000000>; + }; + }; }; &iomuxc {
Sync the device tree with 5.8-rc1. It basically contains the following extra kernel commit: commit 86b08bd5b99480b79a25343f24c1b8c4ddcb5c09 Author: Russell King <rmk+kernel at armlinux.org.uk> Date: Wed Apr 15 16:44:17 2020 +0100 ARM: dts: imx6-sr-som: add ethernet PHY configuration Add ethernet PHY configuration ahead of removing the quirk that configures the clocking mode for the PHY. The RGMII delay is already set correctly. Signed-off-by: Russell King <rmk+kernel at armlinux.org.uk> Reviewed-by: Fabio Estevam <festevam at gmail.com> Signed-off-by: Shawn Guo <shawnguo at kernel.org> , which passes the 'qca,clk-out-frequency' property and it is important to specify the correct frequency generated by the AR8031. Signed-off-by: Fabio Estevam <festevam at gmail.com> Tested-by: Tom Rini <trini at konsulko.com> --- Changes since v1: - None arch/arm/dts/imx6qdl-sr-som.dtsi | 11 +++++++++++ 1 file changed, 11 insertions(+)