| Message ID | 20200618030859.29060-1-festevam@gmail.com |
|---|---|
| State | Superseded |
| Headers | show |
| Series | phy: atheros: ar8035: Fix clock output calculation | expand |
Am 18. Juni 2020 05:08:59 MESZ schrieb Fabio Estevam <festevam at gmail.com>: >The "qca,clk-out-frequency" is calculated incorrectly for AR8035 >due to incorrect masking of priv->clk_25m_reg and priv->clk_25m_mask. > >This same issue has been already fixed in the kernel by: > >commit b1f4c209d84057b6d40b939b6e4404854271d797 >Author: Oleksij Rempel <o.rempel at pengutronix.de> >Date: Wed Apr 1 11:57:32 2020 +0200 > > net: phy: at803x: fix clock sink configuration on ATH8030 and ATH8035 > > The masks in priv->clk_25m_reg and priv->clk_25m_mask are one-bits-set > for the values that comprise the fields, not zero-bits-set. > > This patch fixes the clock frequency configuration for ATH8030 and > ATH8035 Atheros PHYs by removing the erroneous "~". > > To reproduce this bug, configure the PHY with the device tree binding > "qca,clk-out-frequency" and remove the machine specific PHY fixups. > > Fixes: 2f664823a47021 ("net: phy: at803x: add device tree binding") > Signed-off-by: Oleksij Rempel <o.rempel at pengutronix.de> > Reported-by: Russell King <rmk+kernel at armlinux.org.uk> > Reviewed-by: Russell King <rmk+kernel at armlinux.org.uk> > Tested-by: Russell King <rmk+kernel at armlinux.org.uk> > Signed-off-by: David S. Miller <davem at davemloft.net> > >Apply the same fix in the U-Boot driver. > >Tested on a i.MX6 Hummingboard. > >Reported-by: Tom Rini <trini at konsulko.com> >Signed-off-by: Fabio Estevam <festevam at gmail.com> Reviewed-by: Michael Walle <michael at walle.cc> -michael
On Thu, Jun 18, 2020 at 12:08:59AM -0300, Fabio Estevam wrote: > The "qca,clk-out-frequency" is calculated incorrectly for AR8035 > due to incorrect masking of priv->clk_25m_reg and priv->clk_25m_mask. > > This same issue has been already fixed in the kernel by: > > commit b1f4c209d84057b6d40b939b6e4404854271d797 > Author: Oleksij Rempel <o.rempel at pengutronix.de> > Date: Wed Apr 1 11:57:32 2020 +0200 > > net: phy: at803x: fix clock sink configuration on ATH8030 and ATH8035 > > The masks in priv->clk_25m_reg and priv->clk_25m_mask are one-bits-set > for the values that comprise the fields, not zero-bits-set. > > This patch fixes the clock frequency configuration for ATH8030 and > ATH8035 Atheros PHYs by removing the erroneous "~". > > To reproduce this bug, configure the PHY with the device tree binding > "qca,clk-out-frequency" and remove the machine specific PHY fixups. > > Fixes: 2f664823a47021 ("net: phy: at803x: add device tree binding") > Signed-off-by: Oleksij Rempel <o.rempel at pengutronix.de> > Reported-by: Russell King <rmk+kernel at armlinux.org.uk> > Reviewed-by: Russell King <rmk+kernel at armlinux.org.uk> > Tested-by: Russell King <rmk+kernel at armlinux.org.uk> > Signed-off-by: David S. Miller <davem at davemloft.net> > > Apply the same fix in the U-Boot driver. > > Tested on a i.MX6 Hummingboard. > > Reported-by: Tom Rini <trini at konsulko.com> > Signed-off-by: Fabio Estevam <festevam at gmail.com> What else do I need with this to test it myself? This alone doesn't do it (but I'm not surprised) and adding the 2 DM_ETH patches you sent to convert the platform still gives the "Could not get PHY for FEC0: addr 0" error message. Thanks!
Hi Tom, On Thu, Jun 18, 2020 at 10:38 AM Tom Rini <trini at konsulko.com> wrote: > What else do I need with this to test it myself? This alone doesn't do > it (but I'm not surprised) and adding the 2 DM_ETH patches you sent to > convert the platform still gives the "Could not get PHY for FEC0: addr > 0" error message. Thanks! I will submit later today the complete series for you to test.
diff --git a/drivers/net/phy/atheros.c b/drivers/net/phy/atheros.c index 13f7275d17..f922fecd6b 100644 --- a/drivers/net/phy/atheros.c +++ b/drivers/net/phy/atheros.c @@ -275,11 +275,10 @@ static int ar803x_of_init(struct phy_device *phydev) * Fixup for the AR8035 which only has two bits. The two * remaining bits map to the same frequencies. */ - if (phydev->drv->uid == AR8035_PHY_ID) { - u16 clear = AR803x_CLK_25M_MASK & AR8035_CLK_25M_MASK; - priv->clk_25m_mask &= ~clear; - priv->clk_25m_reg &= ~clear; + if (phydev->drv->uid == AR8035_PHY_ID) { + priv->clk_25m_reg &= AR8035_CLK_25M_MASK; + priv->clk_25m_mask &= AR8035_CLK_25M_MASK; } }
The "qca,clk-out-frequency" is calculated incorrectly for AR8035 due to incorrect masking of priv->clk_25m_reg and priv->clk_25m_mask. This same issue has been already fixed in the kernel by: commit b1f4c209d84057b6d40b939b6e4404854271d797 Author: Oleksij Rempel <o.rempel at pengutronix.de> Date: Wed Apr 1 11:57:32 2020 +0200 net: phy: at803x: fix clock sink configuration on ATH8030 and ATH8035 The masks in priv->clk_25m_reg and priv->clk_25m_mask are one-bits-set for the values that comprise the fields, not zero-bits-set. This patch fixes the clock frequency configuration for ATH8030 and ATH8035 Atheros PHYs by removing the erroneous "~". To reproduce this bug, configure the PHY with the device tree binding "qca,clk-out-frequency" and remove the machine specific PHY fixups. Fixes: 2f664823a47021 ("net: phy: at803x: add device tree binding") Signed-off-by: Oleksij Rempel <o.rempel at pengutronix.de> Reported-by: Russell King <rmk+kernel at armlinux.org.uk> Reviewed-by: Russell King <rmk+kernel at armlinux.org.uk> Tested-by: Russell King <rmk+kernel at armlinux.org.uk> Signed-off-by: David S. Miller <davem at davemloft.net> Apply the same fix in the U-Boot driver. Tested on a i.MX6 Hummingboard. Reported-by: Tom Rini <trini at konsulko.com> Signed-off-by: Fabio Estevam <festevam at gmail.com> --- drivers/net/phy/atheros.c | 7 +++---- 1 file changed, 3 insertions(+), 4 deletions(-)